1; RUN: llc -verify-machineinstrs -mtriple=armv7-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-LE 2; RUN: llc -verify-machineinstrs -mtriple=armv7eb-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-BE 3 4define void @ld_st_vec_i8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 5;CHECK-LE-LABEL: ld_st_vec_i8: 6;CHECK-LE: vld1.8 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 7;CHECK-LE-NOT: vrev 8;CHECK-LE: vst1.8 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 9 10;CHECK-BE-LABEL: ld_st_vec_i8: 11;CHECK-BE: vld1.8 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 12;CHECK-BE: vrev64.8 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]] 13;CHECK-BE: vrev64.8 [[Q1]], [[Q2]] 14;CHECK-BE: vst1.8 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 15 16%load = load <16 x i8>, <16 x i8>* %A, align 1 17store <16 x i8> %load, <16 x i8>* %B, align 1 18ret void 19} 20 21define void @ld_st_vec_i16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 22;CHECK-LE-LABEL: ld_st_vec_i16: 23;CHECK-LE: vld1.16 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 24;CHECK-LE-NOT: vrev 25;CHECK-LE: vst1.16 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 26 27;CHECK-BE-LABEL: ld_st_vec_i16: 28;CHECK-BE: vld1.16 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 29;CHECK-BE: vrev64.16 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]] 30;CHECK-BE: vrev64.16 [[Q1]], [[Q2]] 31;CHECK-BE: vst1.16 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 32 33%load = load <8 x i16>, <8 x i16>* %A, align 2 34store <8 x i16> %load, <8 x i16>* %B, align 2 35ret void 36} 37 38define void @ld_st_vec_i32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 39;CHECK-LE-LABEL: ld_st_vec_i32: 40;CHECK-LE: vld1.32 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 41;CHECK-LE-NOT: vrev 42;CHECK-LE: vst1.32 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 43 44;CHECK-BE-LABEL: ld_st_vec_i32: 45;CHECK-BE: vldmia {{r[0-9]+}}, {[[D1:d[0-9]+]], [[D2:d[0-9]+]]} 46;CHECK-BE-NOT: vrev 47;CHECK-BE: vstmia {{r[0-9]+}}, {[[D1]], [[D2]]} 48 49%load = load <4 x i32>, <4 x i32>* %A, align 4 50store <4 x i32> %load, <4 x i32>* %B, align 4 51ret void 52} 53 54define void @ld_st_vec_double(<2 x double>* %A, <2 x double>* %B) nounwind { 55;CHECK-LE-LABEL: ld_st_vec_double: 56;CHECK-LE: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 57;CHECK-LE-NOT: vrev 58;CHECK-LE: vst1.64 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 59 60;CHECK-BE-LABEL: ld_st_vec_double: 61;CHECK-BE: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}] 62;CHECK-BE-NOT: vrev 63;CHECK-BE: vst1.64 {[[D1]], [[D2]]}, [{{r[0-9]+}}] 64 65%load = load <2 x double>, <2 x double>* %A, align 8 66store <2 x double> %load, <2 x double>* %B, align 8 67ret void 68} 69