| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUArgumentUsageInfo.cpp | 66 << " QueuePtr: " << FI.second.QueuePtr in print()
131 return std::make_tuple(QueuePtr ? &QueuePtr : nullptr, in getPreloadedValue()
152 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
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| D | SIMachineFunctionInfo.cpp | 34 QueuePtr(false), in SIMachineFunctionInfo()
152 QueuePtr = true; in SIMachineFunctionInfo()
161 QueuePtr = true; in SIMachineFunctionInfo()
221 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
224 return ArgInfo.QueuePtr.getRegister(); in addQueuePtr()
522 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr); in convertArgumentInfo()
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| D | SIMachineFunctionInfo.h | 189 Optional<SIArgument> QueuePtr;
213 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
401 bool QueuePtr : 1;
625 return QueuePtr;
758 return ArgInfo.QueuePtr.getRegister();
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| D | AMDGPUArgumentUsageInfo.h | 127 ArgDescriptor QueuePtr; member
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| D | AMDGPUTargetMachine.cpp | 1179 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass, in parseMachineFunctionInfo()
1180 MFI->ArgInfo.QueuePtr, 2, 0) || in parseMachineFunctionInfo()
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| D | AMDGPULegalizerInfo.cpp | 1742 Register QueuePtr = MRI.createGenericVirtualRegister( in getSegmentAperture() local
1745 if (!loadInputValue(QueuePtr, B, AMDGPUFunctionArgInfo::QUEUE_PTR)) in getSegmentAperture()
1762 B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset); in getSegmentAperture()
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| D | SIISelLowering.cpp | 1966 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo); in allocateSpecialInputSGPRs()
5218 SDValue QueuePtr = CreateLiveInRegister( in lowerTRAP() local
5222 QueuePtr, SDValue()); in lowerTRAP()
5282 SDValue QueuePtr = CreateLiveInRegister( in getSegmentAperture() local
5290 DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset)); in getSegmentAperture()
5296 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo, in getSegmentAperture()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUArgumentUsageInfo.cpp | 60 << " QueuePtr: " << FI.second.QueuePtr in print()
122 return std::make_pair(QueuePtr ? &QueuePtr : nullptr, in getPreloadedValue()
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| D | SIMachineFunctionInfo.cpp | 33 QueuePtr(false), in SIMachineFunctionInfo()
136 QueuePtr = true; in SIMachineFunctionInfo()
204 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
207 return ArgInfo.QueuePtr.getRegister(); in addQueuePtr()
455 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr); in convertArgumentInfo()
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| D | SIMachineFunctionInfo.h | 189 Optional<SIArgument> QueuePtr;
213 YamlIO.mapOptional("queuePtr", AI.QueuePtr);
390 bool QueuePtr : 1;
600 return QueuePtr;
740 return ArgInfo.QueuePtr.getRegister();
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| D | AMDGPUArgumentUsageInfo.h | 126 ArgDescriptor QueuePtr; member
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| D | AMDGPUTargetMachine.cpp | 1107 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass, in parseMachineFunctionInfo()
1108 MFI->ArgInfo.QueuePtr, 2, 0) || in parseMachineFunctionInfo()
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| D | AMDGPULegalizerInfo.cpp | 1221 Register QueuePtr = MRI.createGenericVirtualRegister( in getSegmentAperture() local
1225 if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr)) in getSegmentAperture()
1245 B.materializePtrAdd(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset); in getSegmentAperture()
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| D | SIISelLowering.cpp | 1743 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo); in allocateSpecialInputSGPRs()
4636 SDValue QueuePtr = CreateLiveInRegister( in lowerTRAP() local
4640 QueuePtr, SDValue()); in lowerTRAP()
4700 SDValue QueuePtr = CreateLiveInRegister( in getSegmentAperture() local
4707 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset); in getSegmentAperture()
4713 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo, in getSegmentAperture()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 94 bool QueuePtr : 1; variable
192 return QueuePtr; in hasQueuePtr()
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| D | SIMachineFunctionInfo.cpp | 70 QueuePtr(false),
129 QueuePtr = true;
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| D | SIISelLowering.cpp | 1449 SDValue QueuePtr = CreateLiveInRegister( in getSegmentAperture() local
1456 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, QueuePtr, in getSegmentAperture()
1466 return DAG.getLoad(MVT::i32, SL, QueuePtr.getValue(1), Ptr, in getSegmentAperture()
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