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/external/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
37 bits<5> RA;
44 let Inst{11-15} = RA;
111 def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
112 "evmra $RT, $RA", IIC_VecFP> {
116 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
117 "brinc $RT, $RA, $RB", IIC_VecFP>;
118 def EVABS : EVXForm_2<520, (outs gprc:$RT), (ins gprc:$RA),
119 "evabs $RT, $RA", IIC_VecFP>;
[all …]
Dp9-instrs.txt63 [PO BF / L RA RB XO /] cmprb BF,L,RA,RB
66 [PO BF // RA RB XO /] cmpeqb BF,RA,RB
71 [PO RS RA /// XO Rc] cnttzw(.) RA,RS
76 [PO RS RA /// XO Rc] cnttzd(.) RA,RS
81 [PO /// L RA RB XO /] copy RA,RB,L
82 copy_first = copy RA, RB, 1
87 [PO /// L RA RB XO Rc] paste(.) RA,RB,L
88 paste_last = paste RA,RB,1
96 [PO RT RA RB RC XO] maddhd RT,RA.RB,RC
99 [PO RT RA RB RC XO] maddhdu RT,RA.RB,RC
[all …]
DPPCInstrHTM.td109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
124 def : Pat<(int_ppc_treclaim i32:$RA),
125 (TRECLAIM $RA)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
38 let RA = 0;
45 bits<5> RA;
50 let Inst{11-15} = RA;
59 bits<5> RA;
65 let Inst{11-15} = RA;
79 let RA = 0;
86 bits<5> RA;
93 let Inst{11-15} = RA;
[all …]
DPPCInstrHTM.td106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
110 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
116 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
121 def : Pat<(int_ppc_treclaim i32:$RA),
122 (TRECLAIM $RA)>;
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
38 let RA = 0;
45 bits<5> RA;
50 let Inst{11-15} = RA;
59 bits<5> RA;
65 let Inst{11-15} = RA;
79 let RA = 0;
86 bits<5> RA;
93 let Inst{11-15} = RA;
[all …]
DPPCInstrHTM.td106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
110 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
116 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
121 def : Pat<(int_ppc_treclaim i32:$RA),
122 (TRECLAIM $RA)>;
/external/llvm-project/llvm/test/CodeGen/X86/
Dcmpxchg-clobber-flags.ll2 …iple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=32-ALL,32-GOOD-RA
3 …386-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=32-…
6 ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %…
8 ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf -pre-RA-sched=fast %s -o - …
27 ; 32-GOOD-RA-LABEL: test_intervening_call:
28 ; 32-GOOD-RA: # %bb.0: # %entry
29 ; 32-GOOD-RA-NEXT: pushl %ebx
30 ; 32-GOOD-RA-NEXT: pushl %esi
31 ; 32-GOOD-RA-NEXT: pushl %eax
32 ; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
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Dfold-call-3.ll5 … RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize | FileCheck %s --check-prefix=…
43 ; pre-RA-LABEL: _Z25RawPointerPerformanceTestPvRN5clang6ActionE:
44 ; pre-RA: ## %bb.0: ## %entry
45 ; pre-RA-NEXT: pushq %rbp
46 ; pre-RA-NEXT: pushq %rbx
47 ; pre-RA-NEXT: subq $24, %rsp
48 ; pre-RA-NEXT: cmpl $0, {{.*}}(%rip)
49 ; pre-RA-NEXT: je LBB0_3
50 ; pre-RA-NEXT: ## %bb.1: ## %bb.nph
51 ; pre-RA-NEXT: movq %rsi, %rbx
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Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '$edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '$esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '$edi', virtual-reg: '' }
19 ; POST-RA-NEXT: - { reg: '$esi', virtual-reg: '' }
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsplitkit-copy-bundle.mir2 …=amdgcn -mcpu=gfx900 -run-pass=greedy -o - -verify-machineinstrs %s | FileCheck -check-prefix=RA %s
3 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=greedy,virtregrewriter,post-RA-sched -o - -verify-m…
12 ; RA-LABEL: name: splitkit_copy_bundle
13 ; RA: bb.0:
14 ; RA: successors: %bb.1(0x80000000)
15 ; RA: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
16 ; RA: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
17 ; RA: undef %5.sub1:sgpr_1024 = S_MOV_B32 -1
18 ; RA: %5.sub0:sgpr_1024 = S_MOV_B32 -1
19 ; RA: undef %4.sub0_sub1:sgpr_1024 = COPY %5.sub0_sub1
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/external/llvm-project/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-ISA31-invalid.txt4 # paddi 1, 2, 8589934591, 1. However, RA is not zero with R=1
8 # plbz 1, 8589934591(2), 1. However, RA is not zero with R=1
12 # plfd 1, 8589934591(2), 1. However, RA is not zero with R=1
16 # plfs 1, 8589934591(2), 1. However, RA is not zero with R=1
20 # plha 1, 8589934591(2), 1. However, RA is not zero with R=1
24 # plhz 1, 8589934591(2), 1. However, RA is not zero with R=1
28 # plwz 1, 8589934591(2), 1. However, RA is not zero with R=1
32 # pstb 1, 8589934591(2), 1. However, RA is not zero with R=1
36 # pstfd 1, 8589934591(2), 1. However, RA is not zero with R=1
40 # pstfs 1, 8589934591(2), 1. However, RA is not zero with R=1
[all …]
/external/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp77 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
78 if (!LiveNodes.count(RA.Id)) in scanInstr()
79 WorkQ.push_back(RA.Id); in scanInstr()
124 auto RA = DFG.addr<RefNode*>(N); in collect() local
125 if (DFG.IsDef(RA)) in collect()
126 processDef(RA, WorkQ); in collect()
128 processUse(RA, WorkQ); in collect()
134 auto RA = DFG.addr<RefNode*>(N); in collect() local
135 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
148 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
[all …]
DRDFGraph.cpp87 void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
89 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
90 << Print<RegisterRef>(RA.Addr->getRegRef(), G) << '>'; in printRefHeader()
91 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
573 bool RegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
574 if (RA == RB) in covers()
576 if (TargetRegisterInfo::isVirtualRegister(RA.Reg)) { in covers()
578 if (RA.Reg != RB.Reg) in covers()
580 if (RA.Sub == 0) in covers()
582 return TRI.composeSubRegIndices(RA.Sub, RB.Sub) == RA.Sub; in covers()
[all …]
DHexagonRDF.cpp19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
20 if (RA == RB) in covers()
23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) && in covers()
26 if (RA.Reg == RB.Reg) { in covers()
27 if (RA.Sub == 0) in covers()
34 return RegisterAliasInfo::covers(RA, RB); in covers()
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dinstructions.h9 #define __COPY(RA, RB, L) \ argument
10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
11 #define COPY(RA, RB, L) \ argument
12 .long __COPY((RA), (RB), (L))
33 #define __PASTE(RA, RB, L, RC) \ argument
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
35 #define PASTE(RA, RB, L, RC) \ argument
36 .long __PASTE((RA), (RB), (L), (RC))
/external/llvm-project/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp88 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
89 if (!LiveNodes.count(RA.Id)) in scanInstr()
90 WorkQ.push_back(RA.Id); in scanInstr()
135 auto RA = DFG.addr<RefNode*>(N); in collect() local
136 if (DFG.IsDef(RA)) in collect()
137 processDef(RA, WorkQ); in collect()
139 processUse(RA, WorkQ); in collect()
145 auto RA = DFG.addr<RefNode*>(N); in collect() local
146 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
159 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp88 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
89 if (!LiveNodes.count(RA.Id)) in scanInstr()
90 WorkQ.push_back(RA.Id); in scanInstr()
135 auto RA = DFG.addr<RefNode*>(N); in collect() local
136 if (DFG.IsDef(RA)) in collect()
137 processDef(RA, WorkQ); in collect()
139 processUse(RA, WorkQ); in collect()
145 auto RA = DFG.addr<RefNode*>(N); in collect() local
146 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
159 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
[all …]
DRDFGraph.cpp108 static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
110 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
111 << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>'; in printRefHeader()
112 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
792 NodeAddr<RefNode*> RA = NA; in cloneNode() local
793 RA.Addr->setReachingDef(0); in cloneNode()
794 RA.Addr->setSibling(0); in cloneNode()
890 for (NodeAddr<RefNode*> RA : IA.Addr->members(*this)) in build()
891 AllRefs.insert(RA.Addr->getRegRef(*this)); in build()
1129 NodeAddr<RefNode*> RA) const { in getRelatedRefs()
[all …]
DRDFRegisters.h115 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
116 if (!isRegMaskId(RA.Reg)) in alias()
117 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
118 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
152 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
166 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
168 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
/external/llvm/test/CodeGen/X86/
Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '%edi' }
19 ; POST-RA-NEXT: - { reg: '%esi' }
/external/clang/test/Layout/
Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
/external/llvm-project/clang/test/Layout/
Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
/external/rust/crates/rayon-core/src/join/
Dmod.rs93 pub fn join<A, B, RA, RB>(oper_a: A, oper_b: B) -> (RA, RB) in join() argument
95 A: FnOnce() -> RA + Send, in join()
97 RA: Send, in join()
115 pub fn join_context<A, B, RA, RB>(oper_a: A, oper_b: B) -> (RA, RB) in join_context() argument
117 A: FnOnce(FnContext) -> RA + Send, in join_context()
119 RA: Send, in join_context()
/external/llvm-project/llvm/lib/CodeGen/
DRDFGraph.cpp108 static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
110 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
111 << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>'; in printRefHeader()
112 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
794 NodeAddr<RefNode*> RA = NA; in cloneNode() local
795 RA.Addr->setReachingDef(0); in cloneNode()
796 RA.Addr->setSibling(0); in cloneNode()
892 for (NodeAddr<RefNode*> RA : IA.Addr->members(*this)) in build()
893 AllRefs.insert(RA.Addr->getRegRef(*this)); in build()
1126 NodeAddr<RefNode*> RA) const { in getRelatedRefs()
[all …]

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