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Searched refs:RDX (Results 1 – 25 of 97) sorted by relevance

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/external/llvm-project/llvm/test/MC/X86/
Dintel-syntax.s17 lea RDX, [8 * RAX + RBX + _foo]
19 lea RDX, [_foo + 8 * RAX + RBX]
21 lea RDX, [8 + RAX * 8 + RCX]
23 lea RDX, [number + 8 * RAX + RCX]
25 lea RDX, [_foo + RAX * 8]
27 lea RDX, [_foo + RAX * 8 + RBX]
29 lea RDX, [RAX - number]
31 lea RDX, [RAX - 8]
33 lea RDX, [RAX + _foo]
35 lea RDX, [RAX + number]
[all …]
Dintel-syntax-error.s30 lea RDX, [unknown_number * RAX + RBX + _foo]
32 lea RDX, [4 * RAX + 27 * RBX + _pat]
34 lea RDX, [[arr]
36 lea RDX, [arr[]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-fp-reduce.ll254 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h
255 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
265 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h
266 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
276 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
277 ; CHECK-NEXT: fadd h0, h0, [[RDX]]
288 ; VBITS_GE_512-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
289 ; VBITS_GE_512-NEXT: fadd h0, h0, [[RDX]]
299 ; VBITS_EQ_256-DAG: fadd h0, h0, [[RDX]]
310 ; VBITS_GE_1024-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping()
295 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
307 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
344 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
380 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
416 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
417 return X86::RDX; in getX86SubSuperRegisterOrZero()
/external/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/
Ddebug_loclists.s13 # REGULAR-NEXT: [0x0000000000000001, 0x0000000000000002): DW_OP_reg1 RDX
14 # VERBOSE-NEXT: [0x0000000000000001, 0x0000000000000002) ".text": DW_OP_reg1 RDX
38 # BOTH-NEXT: DW_LLE_startx_length (0x0000000000000001, 0x0000000000000001): DW_OP_reg1 RDX
/external/llvm/lib/Target/X86/
DX86CallingConv.td41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
186 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
204 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
312 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
374 RDI, RSI, RDX, RCX, R8, R9,
418 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
421 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
427 [RCX , RDX , R8 , R9 ]>>,
476 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
[all …]
DX86InstrArithmetic.td78 // RAX,RDX = RAX*GR64
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
104 // RAX,RDX = RAX*[mem64]
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 // RAX,RDX = RAX*GR64
124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
143 // RAX,RDX = RAX*[mem64]
144 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
306 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86RegisterInfo.td130 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
373 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
375 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
377 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
/external/strace/linux/x86_64/
Darch_regs.h17 #define RDX 12 macro
Duserent.h13 XLAT(8*RDX),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
373 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
395 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
523 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
585 RDI, RSI, RDX, RCX, R8, R9,
640 [RCX , RDX , R8 , R9 ]>>,
653 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
[all …]
DX86InstrArithmetic.td77 // RAX,RDX = RAX*GR64
78 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
81 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>,
101 // RAX,RDX = RAX*[mem64]
102 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
121 // RAX,RDX = RAX*GR64
122 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
139 // RAX,RDX = RAX*[mem64]
140 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
292 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
412 let Defs = [RAX, RDX], Uses = [ECX] in
566 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
572 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
584 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
663 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
724 // RBX/RCX/RDX: Leaf-specific purpose."
731 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
DX86RegisterInfo.td170 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
423 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
447 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
449 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
451 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
471 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
510 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
/external/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
376 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
398 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
427 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
529 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
591 RDI, RSI, RDX, RCX, R8, R9,
646 [RCX , RDX , R8 , R9 ]>>,
659 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
[all …]
DX86InstrArithmetic.td77 // RAX,RDX = RAX*GR64
78 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
81 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>,
101 // RAX,RDX = RAX*[mem64]
102 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
121 // RAX,RDX = RAX*GR64
122 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
139 // RAX,RDX = RAX*[mem64]
140 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
292 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
422 let Defs = [RAX, RDX], Uses = [ECX] in
576 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
582 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
594 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
673 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
734 // RBX/RCX/RDX: Leaf-specific purpose."
741 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
DX86RegisterInfo.td170 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
433 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
457 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
459 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
461 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
481 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
520 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h46 #define RDX 96 macro
/external/llvm-project/llvm/test/tools/llvm-exegesis/X86/
Danalysis-clustering-algorithms.test196 - 'ROL64ri RDX RDX i_0x1'
213 - 'RDX=0x0'
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp159 {codeview::RegisterId::RDX, X86::RDX}, in initLLVMToSEHAndCVRegMapping()
617 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
629 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
666 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
702 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
738 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
739 return X86::RDX; in getX86SubSuperRegisterOrZero()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp157 {codeview::RegisterId::RDX, X86::RDX}, in initLLVMToSEHAndCVRegMapping()
629 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
641 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
678 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
714 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
750 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
751 return X86::RDX; in getX86SubSuperRegisterOrZero()
/external/llvm-project/lldb/test/Shell/SymbolFile/DWARF/
Ddebug_loc.s23 # CHECK: Variable: {{.*}}, name = "x3", type = "int", location = DW_OP_reg1 RDX,
34 # CHECK-NEXT: [0x0000000000000002, 0x0000000000000003): DW_OP_reg1 RDX
Ddwp.s17 # CHECK: Variable: {{.*}}, name = "x", type = "int", location = DW_OP_reg1 RDX
32 …SYMBOLS-NEXT: DW_LLE_startx_length (0x0000000000000003, 0x0000000000000001): DW_OP_reg1 RDX
/external/llvm-project/llvm/test/CodeGen/X86/
D2010-02-23-RematImplicitSubreg.ll6 ; %DL = MOV8rr killed %reg1038, implicit-def %RDX

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