| /external/elfutils/tests/ |
| D | run-pt_gnu_prop-tests.sh | 53 01 [RO: .interp]
54 …02 [RO: .interp .note.gnu.build-id .note.gnu.property .note.ABI-tag .gnu.hash .dynsym .dynstr…
55 03 [RO: .init .plt .plt.sec .text .fini]
56 04 [RO: .rodata .eh_frame_hdr .eh_frame]
59 07 [RO: .note.gnu.build-id .note.gnu.property .note.ABI-tag]
60 08 [RO: .note.gnu.property]
61 09 [RO: .eh_frame_hdr]
104 01 [RO: .interp]
105 …02 [RO: .interp .note.gnu.property .note.gnu.build-id .note.ABI-tag .gnu.hash .dynsym .dynstr…
106 03 [RO: .init .text .fini]
[all …]
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| /external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-isel-globals-ropi-rwpi.ll | 3 …ovt,+v8m -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-MOVT,RO-DEFAULT,RWPI…
4 …no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-NOMOVT,RO-DEFAULT,RWP…
70 ; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:internal_constant
71 ; RO-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:internal_constant
72 ; RO-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
73 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
74 ; RO-DEFAULT-NEXT: bx lr
75 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
76 ; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
96 ; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:external_constant
[all …]
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| D | thumb-isel-globals-ropi-rwpi.ll | 3 …-no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-MOVT,RO-DEFAULT,RWPI…
4 …no-movt -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,RO-DEFAULT-NOMOVT,RO-DEFAULT,RWP…
70 ; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:internal_constant
71 ; RO-DEFAULT-MOVT-NEXT: movt r[[ADDR]], :upper16:internal_constant
72 ; RO-DEFAULT-NOMOVT: ldr r[[ADDR:[0-9]+]], [[LABEL:.L[[:alnum:]_]+]]
73 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
74 ; RO-DEFAULT-NEXT: bx lr
75 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
76 ; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
96 ; RO-DEFAULT-MOVT: movw r[[ADDR:[0-9]+]], :lower16:external_constant
[all …]
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| D | arm-select-globals-ropi-rwpi.mir | 3 …t -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,RO-DEFAULT-MOVT
4 …erify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-NOMOVT,RWPI,RO-DEFAULT-NOMOVT
98 # RO-DEFAULT-NOMOVT: constants:
99 # RO-DEFAULT-NOMOVT: id: 0
100 # RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
106 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
107 …; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 fr…
128 # RO-DEFAULT-NOMOVT: constants:
129 # RO-DEFAULT-NOMOVT: id: 0
130 # RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
[all …]
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| D | thumb-select-globals-ropi-rwpi.mir | 3 …t -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,RO-DEFAULT-MOVT
4 …erify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-NOMOVT,RWPI,RO-DEFAULT-NOMOVT
98 # RO-DEFAULT-NOMOVT: constants:
99 # RO-DEFAULT-NOMOVT: id: 0
100 # RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
106 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant
107 …; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 fro…
128 # RO-DEFAULT-NOMOVT: constants:
129 # RO-DEFAULT-NOMOVT: id: 0
130 # RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
[all …]
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| /external/llvm-project/lld/test/ELF/ |
| D | section-symbol-gap.s | 14 # RUN: llvm-readelf -S -r -s %t.ro | FileCheck %s --check-prefix=RO
30 # RO: [Nr] Name Type Address
31 # RO-NEXT: [ 0]
32 # RO-NEXT: [ 1] .bss NOBITS 0000000000000000
34 # RO: R_X86_64_64 {{.*}} .bss + 1
36 # RO: Symbol table '.symtab' contains 3 entries:
37 # RO-NEXT: Num: Value Size Type Bind Vis Ndx Name
38 # RO-NEXT: 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
39 # RO-NEXT: 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1 .bss
40 # RO-NEXT: 2: 0000000000000000 0 SECTION LOCAL DEFAULT 2 .text
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| D | format-binary.test | 10 # RUN: llvm-readelf -h -S -s -x .data ro | FileCheck --check-prefix=RO %s
12 # RO: Machine: Advanced Micro Devices X86-64
13 # RO: Name Type Address Off Size ES Flg Lk Inf Al
14 # RO-NEXT: NULL 0000000000000000 000000 000000 00 0 0 0
15 # RO-NEXT: .data PROGBITS 0000000000000000 {{.*}} 00000c 00 WA 0 0 8
16 # RO: Value Size Type Bind Vis Ndx Name
17 # RO: 0000000000000000 0 OBJECT GLOBAL DEFAULT 1 _binary_d_t_txt_start
18 # RO-NEXT: 000000000000000c 0 OBJECT GLOBAL DEFAULT 1 _binary_d_t_txt_end
19 # RO-NEXT: 000000000000000c 0 OBJECT GLOBAL DEFAULT ABS _binary_d_t_txt_size
20 # RO: Hex dump of section '.data':
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 186 RegisterOperand RO> :
187 InstSE<(outs), (ins RO:$rs, opnd:$offset),
196 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
198 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
200 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
206 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
208 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
210 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
229 class MovePMM16<string opstr, RegisterOperand RO> :
230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
[all …]
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| D | MipsInstrInfo.td | 1096 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1099 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1101 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1108 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1112 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1114 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1130 class LogicNOR<string opstr, RegisterOperand RO>:
1131 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1133 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1139 RegisterOperand RO, InstrItinClass itin,
[all …]
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| D | MicroMips64r6InstrInfo.td | 96 class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
99 dag OutOperandList = (outs RO:$rt);
100 dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
102 list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
173 class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
177 dag OutOperandList = (outs RO:$rd);
178 dag InOperandList = (ins RO:$rs, RO:$rt);
180 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 199 RegisterOperand RO> :
200 InstSE<(outs), (ins RO:$rs, opnd:$offset),
209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
211 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
224 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
[all …]
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| D | MipsInstrInfo.td | 1313 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1316 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1318 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1325 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1329 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1347 class LogicNOR<string opstr, RegisterOperand RO>:
1348 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1350 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1356 RegisterOperand RO, InstrItinClass itin,
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 199 RegisterOperand RO> :
200 InstSE<(outs), (ins RO:$rs, opnd:$offset),
209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
211 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
224 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
[all …]
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| D | MipsInstrInfo.td | 1313 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1316 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1318 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1325 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1329 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1347 class LogicNOR<string opstr, RegisterOperand RO>:
1348 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1350 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1356 RegisterOperand RO, InstrItinClass itin,
[all …]
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| /external/ltp/testcases/kernel/fs/fs_readonly/ |
| D | test_robind.sh | 143 local RO=$3
158 if [ "$RO" = "false" -a $tst_result -ne 0 -o "$RO" = "true" -a \
163 $dir $fs_type read-only flag: $RO"
166 $dir $fs_type read-only flag: $RO"
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| /external/autotest/server/site_tests/firmware_Fingerprint/ |
| D | control.reboot_to_ro | 10 Validates that booting into RO fingerprint firmware succeeds.
13 Fails if unable to boot into RO fingerprint firmware.
24 Attempts to reboot into RO firmware and validates that it succeeds. Then
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| D | control.rw_no_update_ro | 10 Verify HW write protect prevents RO fingerprint firmware modification.
13 Fails if the RO firmware can be written while HW write protect is enabled.
27 Enables hardware write protect, attempts to flash the RO fingerprint firmware,
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| D | control.ro_only_boots_valid_rw | 10 Verify the RO fingerprint firmware only boots valid RW firmware.
13 Fails if the RO firmware boots invalid RW firmware.
29 flash successfully, but fail to boot (i.e., stay in RO mode). Finally, it
|
| /external/arm-trusted-firmware/docs/security_advisories/ |
| D | security-advisory-tfv-3.rst | 5 | Title | RO memory is always executable at AArch64 Secure EL1 |
32 Read-Only (RO), non-executable memory region.
35 Any memory region mapped as RO will always be executable, regardless of whether
41 platforms. The RO data section for these images on these platforms is
47 permissions separately to data access permissions. All RO normal memory regions
49 would only manifest itself for device memory mapped as RO; use of this mapping
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | CFIInstrInserter.cpp | 365 CSRSavedLocation RO = it->second; in insertCFIInstrs() local
366 if (!RO.Reg && RO.Offset) { in insertCFIInstrs()
368 MCCFIInstruction::createOffset(nullptr, Reg, *RO.Offset)); in insertCFIInstrs()
369 } else if (RO.Reg && !RO.Offset) { in insertCFIInstrs()
371 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
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| /external/autotest/test_suites/ |
| D | control.faft_bios_ro_qual | 7 PURPOSE = "Qualify the AP firmware for RO+RW release"
15 This test suite verifies if the AP firmware is ready for RO+RW production
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| /external/autotest/server/site_tests/firmware_FWupdate/ |
| D | control.new | 13 RO+RW firmware update using chromeos-firmwareupdate --mode=recovery
14 This variant is RO=new, RW=new.
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| D | control.upgrade_rw | 13 RO+RW firmware update using chromeos-firmwareupdate --mode=recovery
14 This variant is RO=old, RW=new.
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| D | control.downgrade_rw | 13 RO+RW firmware update using chromeos-firmwareupdate --mode=recovery
14 This variant is RO=old, RW=old->new->old.
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| /external/arm-trusted-firmware/plat/nvidia/tegra/scat/ |
| D | bl31.scat | 31 .ANY1(+RO-CODE)
45 .ANY2(+RO-DATA)
72 * Keep the .got section in the RO section as it is patched
73 * prior to enabling the MMU and having the .got in RO is better for
|