| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.rsq.clamp.ll | 11 ; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], [[SRC]]
12 ; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
30 ; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}
31 ; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
|
| D | rsq.ll | 80 ; SI-SAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
81 ; SI-SAFE: buffer_store_dword [[RSQ]]
84 ; SI-UNSAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
85 ; SI-UNSAFE: buffer_store_dword [[RSQ]]
111 ; SI-SAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
112 ; SI-SAFE: buffer_store_dword [[RSQ]]
115 ; SI-UNSAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
116 ; SI-UNSAFE: buffer_store_dword [[RSQ]]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.rsq.clamp.ll | 11 ; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], [[SRC]]
12 ; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
31 ; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}
32 ; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
|
| D | llvm.AMDGPU.rsq.clamped.f64.ll | 9 ; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}]
13 ; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
|
| D | llvm.AMDGPU.rsq.clamped.ll | 13 ; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}}
14 ; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
|
| /external/mesa3d/src/gallium/tests/graw/fragment-shader/ |
| D | frag-rsq.sh | 12 RSQ TEMP[0].x, TEMP[0].xxxx
|
| /external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
| D | vert-rsq.sh | 14 RSQ TEMP[0].x, TEMP[0].xxxx
|
| /external/igt-gpu-tools/lib/ |
| D | i915_3d.h | 538 i915_fs_arith_masked (RSQ, dest_reg, dest_mask, \
543 i915_fs_arith (RSQ, dest_reg, \
|
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 63 OP11(RSQ)
|
| /external/mesa3d/docs/relnotes/ |
| D | 10.2.3.rst | 68 - radeon/llvm: Use the llvm.rsq.clamped intrinsic for RSQ
|
| D | 10.4.3.rst | 67 - st/nine: Handle RSQ special cases
|
| D | 8.0.5.rst | 218 - r600g: fix RSQ of negative value on Cayman
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 44 OP11(RSQ)
|
| D | tgsi_info_opcodes.h | 5 OPCODE(1, 1, REPL, RSQ)
|
| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 222 RSQ{sat} { return_opcode( 1, SCALAR_OP, RSQ, 3); }
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 256 RSQ, enumerator
|
| D | AMDGPUInstrInfo.td | 65 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_emit.c | 68 OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
|
| D | etnaviv_disasm.c | 476 OPC(RSQ),
|
| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 403 "rsq" { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; }
|
| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 154 rsq { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; }
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 418 RSQ, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 406 RSQ, enumerator
|
| /external/virglrenderer/tests/ |
| D | large_shader.h | 46 14: RSQ TEMP[2].x, TEMP[2].xxxx
58 26: RSQ TEMP[8].x, TEMP[7].xxxx
347 315: RSQ TEMP[7].x, TEMP[6].xxxx
610 578: RSQ TEMP[9].x, TEMP[8].xxxx
875 843: RSQ TEMP[10].x, TEMP[9].xxxx
1141 1109: RSQ TEMP[9].x, TEMP[2].xxxx
1403 1371: RSQ TEMP[2].x, TEMP[2].xxxx
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qir.h | 708 QIR_ALU1(RSQ) in QIR_ALU1()
|