1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains DAG node defintions for the AMDGPU target. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// AMDGPU DAG Profiles 16//===----------------------------------------------------------------------===// 17 18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [ 19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 20]>; 21 22def AMDGPUTrigPreOp : SDTypeProfile<1, 2, 23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>] 24>; 25 26def AMDGPULdExpOp : SDTypeProfile<1, 2, 27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>] 28>; 29 30def AMDGPUFPClassOp : SDTypeProfile<1, 2, 31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>] 32>; 33 34def AMDGPUDivScaleOp : SDTypeProfile<2, 3, 35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>] 36>; 37 38// float, float, float, vcc 39def AMDGPUFmasOp : SDTypeProfile<1, 4, 40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>] 41>; 42 43//===----------------------------------------------------------------------===// 44// AMDGPU DAG Nodes 45// 46 47def AMDGPUconstdata_ptr : SDNode< 48 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>, 49 SDTCisVT<0, iPTR>]> 50>; 51 52// This argument to this node is a dword address. 53def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>; 54 55def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>; 56def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>; 57 58// out = a - floor(a) 59def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; 60 61// out = 1.0 / a 62def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>; 63 64// out = 1.0 / sqrt(a) 65def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>; 66 67// out = 1.0 / sqrt(a) 68def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>; 69 70// out = 1.0 / sqrt(a) result clamped to +/- max_float. 71def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>; 72 73def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>; 74 75def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>; 76 77// out = max(a, b) a and b are floats, where a nan comparison fails. 78// This is not commutative because this gives the second operand: 79// x < nan ? x : nan -> nan 80// nan < x ? nan : x -> x 81def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp, 82 [] 83>; 84 85def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>; 86 87// out = max(a, b) a and b are signed ints 88def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, 89 [SDNPCommutative, SDNPAssociative] 90>; 91 92// out = max(a, b) a and b are unsigned ints 93def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp, 94 [SDNPCommutative, SDNPAssociative] 95>; 96 97// out = min(a, b) a and b are floats, where a nan comparison fails. 98def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp, 99 [] 100>; 101 102// FIXME: TableGen doesn't like commutative instructions with more 103// than 2 operands. 104// out = max(a, b, c) a, b and c are floats 105def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp, 106 [/*SDNPCommutative, SDNPAssociative*/] 107>; 108 109// out = max(a, b, c) a, b, and c are signed ints 110def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp, 111 [/*SDNPCommutative, SDNPAssociative*/] 112>; 113 114// out = max(a, b, c) a, b and c are unsigned ints 115def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp, 116 [/*SDNPCommutative, SDNPAssociative*/] 117>; 118 119// out = min(a, b, c) a, b and c are floats 120def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp, 121 [/*SDNPCommutative, SDNPAssociative*/] 122>; 123 124// out = min(a, b, c) a, b and c are signed ints 125def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp, 126 [/*SDNPCommutative, SDNPAssociative*/] 127>; 128 129// out = min(a, b) a and b are unsigned ints 130def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp, 131 [/*SDNPCommutative, SDNPAssociative*/] 132>; 133 134// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0 135def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>; 136 137// out = (src1 > src0) ? 1 : 0 138def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>; 139 140 141def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0", 142 SDTIntToFPOp, []>; 143def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1", 144 SDTIntToFPOp, []>; 145def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2", 146 SDTIntToFPOp, []>; 147def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3", 148 SDTIntToFPOp, []>; 149 150 151// urecip - This operation is a helper for integer division, it returns the 152// result of 1 / a as a fractional unsigned integer. 153// out = (2^32 / a) + e 154// e is rounding error 155def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; 156 157// Special case divide preop and flags. 158def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>; 159 160// Special case divide FMA with scale and flags (src0 = Quotient, 161// src1 = Denominator, src2 = Numerator). 162def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>; 163 164// Single or double precision division fixup. 165// Special case divide fixup and flags(src0 = Quotient, src1 = 166// Denominator, src2 = Numerator). 167def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>; 168 169// Look Up 2.0 / pi src0 with segment select src1[4:0] 170def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>; 171 172def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD", 173 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 174 [SDNPHasChain, SDNPMayLoad]>; 175 176def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE", 177 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>, 178 [SDNPHasChain, SDNPMayStore]>; 179 180// MSKOR instructions are atomic memory instructions used mainly for storing 181// 8-bit and 16-bit values. The definition is: 182// 183// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src) 184// 185// src0: vec4(src, 0, 0, mask) 186// src1: dst - rat offset (aka pointer) in dwords 187def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR", 188 SDTypeProfile<0, 2, []>, 189 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 190 191def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP", 192 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>, 193 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 194 SDNPMemOperand]>; 195 196def AMDGPUround : SDNode<"ISD::FROUND", 197 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>; 198 199def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>; 200def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>; 201def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>; 202def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>; 203 204def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>; 205 206// Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when 207// performing the mulitply. The result is a 32-bit value. 208def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp, 209 [SDNPCommutative] 210>; 211def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp, 212 [SDNPCommutative] 213>; 214 215def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp, 216 [] 217>; 218def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp, 219 [] 220>; 221 222def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp, 223 [] 224>; 225 226def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp, 227 [] 228>; 229 230def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>; 231 232def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG", 233 SDTypeProfile<0, 1, [SDTCisInt<0>]>, 234 [SDNPHasChain, SDNPInGlue]>; 235 236def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV", 237 SDTypeProfile<1, 3, [SDTCisFP<0>]>, 238 [SDNPInGlue]>; 239 240def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1", 241 SDTypeProfile<1, 3, [SDTCisFP<0>]>, 242 [SDNPInGlue, SDNPOutGlue]>; 243 244def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2", 245 SDTypeProfile<1, 4, [SDTCisFP<0>]>, 246 [SDNPInGlue]>; 247 248//===----------------------------------------------------------------------===// 249// Flow Control Profile Types 250//===----------------------------------------------------------------------===// 251// Branch instruction where second and third are basic blocks 252def SDTIL_BRCond : SDTypeProfile<0, 2, [ 253 SDTCisVT<0, OtherVT> 254 ]>; 255 256//===----------------------------------------------------------------------===// 257// Flow Control DAG Nodes 258//===----------------------------------------------------------------------===// 259def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; 260 261//===----------------------------------------------------------------------===// 262// Call/Return DAG Nodes 263//===----------------------------------------------------------------------===// 264def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone, 265 [SDNPHasChain, SDNPOptInGlue]>; 266 267def AMDGPUreturn : SDNode<"AMDGPUISD::RETURN", SDTNone, 268 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 269