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Searched refs:RSQRT (Results 1 – 25 of 34) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/InstCombine/
Dfmul-sqrt.ll105 ; CHECK-NEXT: [[RSQRT:%.*]] = fdiv double 1.000000e+00, [[SQRT]]
107 ; CHECK-NEXT: store double [[RSQRT]], double* [[P:%.*]], align 8
121 ; CHECK-NEXT: [[RSQRT:%.*]] = fdiv fast <2 x float> <float 1.000000e+00, float 1.000000e+00>, [[…
123 ; CHECK-NEXT: store <2 x float> [[RSQRT]], <2 x float>* [[P:%.*]], align 8
213 ; CHECK-NEXT: [[RSQRT:%.*]] = fdiv fast double 1.000000e+00, [[SQRT]]
214 ; CHECK-NEXT: call void @use(double [[RSQRT]])
215 ; CHECK-NEXT: [[SQUARED:%.*]] = fmul fast double [[RSQRT]], [[RSQRT]]
/external/tensorflow/tensorflow/lite/delegates/gpu/gl/kernels/
Delementwise.cc75 case OperationType::RSQRT: in GenerateCode()
235 case OperationType::RSQRT: in NewElementwiseNodeShader()
Dregistry.cc110 insert_elementwise_op(Type::RSQRT); in Registry()
Delementwise_test.cc145 OperationType op_type = OperationType::RSQRT; in TEST()
/external/tensorflow/tensorflow/cc/gradients/
Dmath_grad_test.cc67 RSQRT, enumerator
127 case RSQRT: in TestCWiseGrad()
278 TestCWiseGrad<float, float>(RSQRT, x_fn); in TEST_F()
285 TestCWiseGrad<complex64, complex64>(RSQRT, x_fn); in TEST_F()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedExynosM4.td670 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
671 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
673 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>;
674 def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>;
820 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
821 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
822 def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
823 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>;
824 def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
DAArch64SchedExynosM5.td728 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
730 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
857 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
858 def : InstRW<[M5WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
859 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
DAArch64SchedExynosM3.td553 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>;
556 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
673 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
675 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>;
DAArch64SchedA57.td515 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
517 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
520 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
522 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedExynosM4.td669 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
670 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
672 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>;
673 def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>;
819 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
820 def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
821 def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
822 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>;
823 def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
DAArch64SchedExynosM5.td727 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
729 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
856 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
857 def : InstRW<[M5WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
858 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
DAArch64SchedExynosM3.td552 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>;
555 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
672 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
674 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>;
DAArch64SchedA57.td514 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
516 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
519 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
521 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
Dprepare-tf.mlir85 // CHECK: %[[RSQRT:.*]] = "tf.Rsqrt"(%[[ADD1]])
87 // CHECK: %[[MUL1:.*]] = "tf.Mul"(%[[ARG1:.*]], %[[RSQRT]])
110 // CHECK: %[[RSQRT:.*]] = "tf.Rsqrt"(%[[VARIANCE]])
111 // CHECK: %[[MUL1:.*]] = "tf.Mul"(%[[ARG_T:.*]], %[[RSQRT]])
112 // CHECK: %[[MUL2:.*]] = "tf.Mul"(%[[ARG_M:.*]], %[[RSQRT]])
125 // CHECK: %[[RSQRT:.*]] = "tf.Rsqrt"(%[[VARIANCE]])
126 // CHECK: %[[MUL0:.*]] = "tf.Mul"(%[[RSQRT]], %[[ARG_GAMMA:.*]])
800 // CHECK: %[[RSQRT:.*]] = "tf.Rsqrt"(%[[ADD]]) : (tensor<2xf32>) -> tensor<2xf32>
801 …// CHECK: %[[MUL1:.*]] = "tf.Mul"(%arg1, %[[RSQRT]]) : (tensor<2xf32>, tensor<2xf32>) -> tensor<2…
/external/llvm-project/mlir/test/Dialect/Linalg/
Dvectorization.mlir197 // CHECK: %[[RSQRT:.*]] = rsqrt %[[V3]] : vector<4x256xf32>
207 // CHECK: vector.transfer_write %[[RSQRT]], %[[ARG0]][%[[C0]], %[[C0]]] {{.*}} : vector<4x2…
/external/llvm/lib/Target/AArch64/
DAArch64SchedM1.td326 def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev")>;
327 def : InstRW<[M1WriteNMISC1], (instregex "^[FU](RECP|RSQRT)Xv")>;
328 def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)Sv")>;
DAArch64SchedA57.td511 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
513 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
516 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
518 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
/external/tensorflow/tensorflow/lite/delegates/gpu/common/tasks/
Delementwise.cc74 case OperationType::RSQRT: in GetOneInputCode()
/external/tensorflow/tensorflow/lite/delegates/gpu/common/
Doperations.h81 RSQRT, enumerator
Doperations.cc165 case OperationType::RSQRT: in ToString()
245 {"rsqrt", OperationType::RSQRT}, in OperationTypeFromString()
Dmodel_builder.cc708 case OperationType::RSQRT: in IsOneArgumentOperation()
2410 return std::make_unique<ElementwiseOperationParser>(OperationType::RSQRT); in NewOperationParser()
/external/tensorflow/tensorflow/lite/delegates/gpu/common/selectors/
Doperation_selector.cc513 case OperationType::RSQRT: in GPUOperationFromNode()
/external/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h1168 VIR_SFU(RSQRT) in VIR_A_ALU2()
/external/llvm/lib/Target/X86/
DX86SchedHaswell.td2076 // RSQRT SS/PS.
2081 def : InstRW<[WriteRSQRTr], (instregex "(V?)RSQRT(SS|PS)r(_Int)?")>;
2089 def : InstRW<[WriteRSQRTm], (instregex "(V?)RSQRT(SS|PS)m(_Int)?")>;
/external/tensorflow/tensorflow/lite/schema/
Dschema_v3a.fbs303 RSQRT = 76,

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