| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrAlias.td | 43 // Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44 def : InstAlias<"memb($Rs) = $Rt",
45 (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
47 def : InstAlias<"memh($Rs) = $Rt",
48 (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
50 def : InstAlias<"memh($Rs) = $Rt.h",
51 (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
53 def : InstAlias<"memw($Rs) = $Rt",
54 (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
56 def : InstAlias<"memb($Rs) = $Rt.new",
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| D | HexagonIsetDx.td | 82 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
83 "memb($Rs + #$u4_0)=#0"> {
84 bits<4> Rs;
88 let Inst{7-4} = Rs;
109 (ins IntRegs:$Rs, u3_1Imm:$u3_1),
110 "$Rd = memuh($Rs + #$u3_1)"> {
112 bits<4> Rs;
117 let Inst{7-4} = Rs;
151 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
152 "$Rd = memub($Rs + #$u4_0)"> {
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| D | HexagonInstrInfoVector.td | 89 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
93 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
151 def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
152 (S2_asr_i_vw V2I32:$Rs, imm:$u5)>;
153 def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4ImmPred:$u4)),
154 (S2_asr_i_vh V4I16:$Rs, imm:$u4)>;
155 def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
156 (S2_lsr_i_vw V2I32:$Rs, imm:$u5)>;
157 def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4ImmPred:$u4)),
158 (S2_lsr_i_vh V4I16:$Rs, imm:$u4)>;
[all …]
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| D | HexagonSystemInst.td | 23 bits<5> Rs;
30 let Inst{20-16} = Rs;
41 bits<5> Rs;
48 let Inst{20-16} = Rs;
54 let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in {
61 def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>;
63 def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>;
65 def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
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| D | HexagonIntrinsics.td | 21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
25 : Pat <(IntID I64:$Rs),
26 (MI I64:$Rs)>;
34 : Pat<(IntID I32:$Rs, ImmPred:$It),
35 (MI I32:$Rs, ImmPred:$It)>;
43 : Pat<(IntID I64:$Rs, imm:$It),
44 (MI I64:$Rs, imm:$It)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
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| D | HexagonInstrInfo.td | 30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
128 bits<5> Rs;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
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| D | HexagonInstrInfoV4.td | 131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
175 bits<5> Rs;
180 let Inst{20-16} = Rs;
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | alu64.ll | 5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | alu64.ll | 5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsics.td | 12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
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| D | HexagonPatterns.td | 46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
249 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
250 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
251 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
252 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
253 def ToAext64: OutPatFrag<(ops node:$Rs),
254 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
256 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
234 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
235 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
236 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
237 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
238 def ToAext64: OutPatFrag<(ops node:$Rs),
239 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
241 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
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| D | HexagonIntrinsics.td | 12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
[all …]
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-shift-rs-t32.json | 28 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs>
29 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
30 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs>
31 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs>
32 // MNEMONIC{<c>}.W <Rd>, <Rm>, <shift> <Rs>
36 "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
37 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
38 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
39 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
40 // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
33 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
[all …]
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| D | cond-rd-rn-operand-rm-t32.json | 121 // TODO: Add tests for MOV <Rd>, <Rn>, <shift>, <Rs>.
122 "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
123 // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
125 "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
126 // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
128 "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
129 // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
131 "Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
132 // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
134 "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
[all …]
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| D | cond-rd-operand-rn-shift-rs-a32.json | 29 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1
30 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1
31 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
33 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1
36 "Tst" // TST{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1
|
| /external/mesa3d/src/gallium/frontends/clover/util/ |
| D | algorithm.hpp | 75 template<typename... Rs>
76 adaptor_range<zips, Rs...>
77 zip(Rs &&... rs) { in zip()
78 return map(zips(), std::forward<Rs>(rs)...); in zip()
101 template<typename F, typename... Rs>
103 for_each(F &&f, Rs &&... rs) { in for_each()
104 eval(map(std::forward<F>(f), std::forward<Rs>(rs)...)); in for_each()
172 template<typename F, typename... Rs>
174 all_of(F &&f, Rs &&... rs) { in all_of()
187 template<typename F, typename... Rs>
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; in getCompoundInsn() local
229 Rs = L.getOperand(1); in getCompoundInsn()
235 CompoundInsn->addOperand(Rs); in getCompoundInsn()
242 Rs = L.getOperand(1); in getCompoundInsn()
248 CompoundInsn->addOperand(Rs); in getCompoundInsn()
255 Rs = L.getOperand(1); in getCompoundInsn()
261 CompoundInsn->addOperand(Rs); in getCompoundInsn()
268 Rs = L.getOperand(1); in getCompoundInsn()
274 CompoundInsn->addOperand(Rs); in getCompoundInsn()
289 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
222 Rs = L.getOperand(1); in getCompoundInsn()
228 CompoundInsn->addOperand(Rs); in getCompoundInsn()
235 Rs = L.getOperand(1); in getCompoundInsn()
241 CompoundInsn->addOperand(Rs); in getCompoundInsn()
248 Rs = L.getOperand(1); in getCompoundInsn()
254 CompoundInsn->addOperand(Rs); in getCompoundInsn()
261 Rs = L.getOperand(1); in getCompoundInsn()
267 CompoundInsn->addOperand(Rs); in getCompoundInsn()
282 Rs = L.getOperand(1); in getCompoundInsn()
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| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
223 Rs = L.getOperand(1); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
268 CompoundInsn->addOperand(Rs); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
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| /external/llvm-project/clang/test/Sema/ |
| D | builtins-hexagon-v65.c | 5 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
6 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
9 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
10 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
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| D | builtins-hexagon-v62.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
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| D | builtins-hexagon-v60.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
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| D | builtins-hexagon-v55.c | 7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60() argument
9 return __builtin_HEXAGON_S6_rol_i_r(Rs, 3); in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62() argument
16 return __builtin_HEXAGON_S6_vsplatrbp(Rs); in builtin_needs_v62()
|