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Searched refs:SLOT2 (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV55.td21 // | SLOT2 | XTYPE ALU32 J JR |
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
59 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
60 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
[all …]
DHexagonScheduleV60.td71 // | SLOT2 | XTYPE ALU32 J JR |
107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
125 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
126 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
[all …]
DHexagonScheduleV4.td21 // | SLOT2 | XTYPE ALU32 J JR |
29 def SLOT2 : FuncUnit;
100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td185 InstrItinData <tc_002cb246, [InstrStage<1, [SLOT2, SLOT3]>]>,
187 InstrItinData <tc_05c070ec, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
188 InstrItinData <tc_05d3a09b, [InstrStage<1, [SLOT2, SLOT3]>]>,
189 InstrItinData <tc_0663f615, [InstrStage<1, [SLOT2, SLOT3]>]>,
192 InstrItinData <tc_0ae0825c, [InstrStage<1, [SLOT2, SLOT3]>]>,
195 InstrItinData <tc_13bfbcf9, [InstrStage<1, [SLOT2, SLOT3]>]>,
197 InstrItinData <tc_14b5c689, [InstrStage<1, [SLOT2, SLOT3]>]>,
201 InstrItinData <tc_1a2fd869, [InstrStage<1, [SLOT2, SLOT3]>]>,
202 InstrItinData <tc_1ad90acd, [InstrStage<1, [SLOT2]>]>,
203 InstrItinData <tc_1ae57e39, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
[all …]
DHexagonDepIICHVX.td106 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
123 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
128 [InstrStage<1, [SLOT2, SLOT3], 0>,
133 [InstrStage<1, [SLOT2, SLOT3], 0>,
138 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
150 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
155 [InstrStage<1, [SLOT2, SLOT3], 0>,
161 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
172 [InstrStage<1, [SLOT2, SLOT3], 0>,
188 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
32 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
DHexagonScheduleV60.td20 // | SLOT2 | XTYPE ALU32 J JR |
64 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV62.td20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
DHexagonScheduleV66.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td221 InstrItinData <tc_01d44cb2, [InstrStage<1, [SLOT2, SLOT3]>]>,
222 InstrItinData <tc_01e1be3b, [InstrStage<1, [SLOT2, SLOT3]>]>,
223 InstrItinData <tc_02fe1c65, [InstrStage<1, [SLOT2, SLOT3]>]>,
226 InstrItinData <tc_0a195f2c, [InstrStage<1, [SLOT2, SLOT3]>]>,
228 InstrItinData <tc_0ba0d5da, [InstrStage<1, [SLOT2]>]>,
229 InstrItinData <tc_0dfac0a7, [InstrStage<1, [SLOT2, SLOT3]>]>,
232 InstrItinData <tc_10b884b7, [InstrStage<1, [SLOT2]>]>,
233 InstrItinData <tc_112d30d6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
237 InstrItinData <tc_151bf368, [InstrStage<1, [SLOT2, SLOT3]>]>,
242 InstrItinData <tc_1c2c7a4a, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
[all …]
DHexagonDepIICHVX.td106 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
123 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
128 [InstrStage<1, [SLOT2, SLOT3], 0>,
133 [InstrStage<1, [SLOT2, SLOT3], 0>,
138 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
150 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
155 [InstrStage<1, [SLOT2, SLOT3], 0>,
161 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
172 [InstrStage<1, [SLOT2, SLOT3], 0>,
188 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
32 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV67T.td11 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
13 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
14 InstrStage<1, [SLOT2, SLOT3]>],
44 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
DHexagonScheduleV60.td20 // | SLOT2 | XTYPE ALU32 J JR |
64 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
DHexagonScheduleV62.td20 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV67.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV66.td22 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dbr-cond-not-merge.ll67 ; NOOPT: str w1, [sp, #[[SLOT2:[0-9]+]]]
74 ; NOOPT: ldr [[R3:w[0-9]+]], [sp, #[[SLOT2]]]

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