/external/llvm/unittests/Support/ |
D | ScaledNumberTest.cpp | 39 typedef ScaledPair<uint32_t> SP32; typedef 43 EXPECT_EQ(getRounded32(0, 0, false), SP32(0, 0)); in TEST() 44 EXPECT_EQ(getRounded32(0, 0, true), SP32(1, 0)); in TEST() 45 EXPECT_EQ(getRounded32(20, 21, true), SP32(21, 21)); in TEST() 46 EXPECT_EQ(getRounded32(UINT32_MAX, 0, false), SP32(UINT32_MAX, 0)); in TEST() 47 EXPECT_EQ(getRounded32(UINT32_MAX, 0, true), SP32(1 << 31, 1)); in TEST() 60 EXPECT_EQ(getAdjusted32(0), SP32(0, 0)); in TEST() 61 EXPECT_EQ(getAdjusted32(0, 5), SP32(0, 5)); in TEST() 62 EXPECT_EQ(getAdjusted32(UINT32_MAX), SP32(UINT32_MAX, 0)); in TEST() 63 EXPECT_EQ(getAdjusted32(Max32In64 << 1), SP32(UINT32_MAX, 1)); in TEST() [all …]
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/external/llvm-project/llvm/unittests/Support/ |
D | ScaledNumberTest.cpp | 38 typedef ScaledPair<uint32_t> SP32; typedef 42 EXPECT_EQ(getRounded32(0, 0, false), SP32(0, 0)); in TEST() 43 EXPECT_EQ(getRounded32(0, 0, true), SP32(1, 0)); in TEST() 44 EXPECT_EQ(getRounded32(20, 21, true), SP32(21, 21)); in TEST() 45 EXPECT_EQ(getRounded32(UINT32_MAX, 0, false), SP32(UINT32_MAX, 0)); in TEST() 46 EXPECT_EQ(getRounded32(UINT32_MAX, 0, true), SP32(1 << 31, 1)); in TEST() 59 EXPECT_EQ(getAdjusted32(0), SP32(0, 0)); in TEST() 60 EXPECT_EQ(getAdjusted32(0, 5), SP32(0, 5)); in TEST() 61 EXPECT_EQ(getAdjusted32(UINT32_MAX), SP32(UINT32_MAX, 0)); in TEST() 62 EXPECT_EQ(getAdjusted32(Max32In64 << 1), SP32(UINT32_MAX, 1)); in TEST() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyFrameLowering.cpp | 147 writeSPToGlobal(WebAssembly::SP32, MF, MBB, I, DL); in eliminateCallFramePseudoInstr() 174 unsigned SPReg = WebAssembly::SP32; in emitPrologue() 197 WebAssembly::SP32) in emitPrologue() 209 WebAssembly::SP32) in emitPrologue() 210 .addReg(WebAssembly::SP32) in emitPrologue() 218 .addReg(WebAssembly::SP32); in emitPrologue() 221 writeSPToGlobal(WebAssembly::SP32, MF, MBB, InsertPt, DL); in emitPrologue() 254 .addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32) in emitEpilogue() 257 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32; in emitEpilogue()
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D | WebAssemblyInstrCall.td | 19 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in { 24 } // Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 57 let Uses = [SP32, SP64], isCall = 1 in { 119 } // Uses = [SP32,SP64], isCall = 1
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D | WebAssemblyRegisterInfo.td | 32 def SP32 : WebAssemblyReg<"%SP32">; 61 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
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D | WebAssemblyRegisterInfo.cpp | 47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs() 137 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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D | WebAssemblyLateEHPrepare.cpp | 387 FrameLowering->writeSPToGlobal(WebAssembly::SP32, MF, MBB, InsertPos, in restoreStackPointer()
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D | WebAssemblyISelLowering.cpp | 53 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyRegisterInfo.cpp | 48 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs() 76 .ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false); in eliminateFrameIndex() 97 .ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false); in eliminateFrameIndex() 107 unsigned FIRegOperand = WebAssembly::SP32; in eliminateFrameIndex() 119 .addReg(WebAssembly::SP32) in eliminateFrameIndex() 129 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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D | WebAssemblyFrameLowering.cpp | 117 writeSPToMemory(WebAssembly::SP32, MF, MBB, I, I, DL); in eliminateCallFramePseudoInstr() 151 StackSize ? SPReg : (unsigned)WebAssembly::SP32) in emitPrologue() 163 WebAssembly::SP32) in emitPrologue() 173 .addReg(WebAssembly::SP32); in emitPrologue() 176 writeSPToMemory(WebAssembly::SP32, MF, MBB, InsertPt, InsertPt, DL); in emitPrologue() 208 .addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32) in emitEpilogue() 211 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32; in emitEpilogue()
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D | WebAssemblyInstrCall.td | 21 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in { 36 let Uses = [SP32, SP64], isCall = 1 in { 48 } // Uses = [SP32,SP64], isCall = 1
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D | WebAssemblyRegisterInfo.td | 33 def SP32 : WebAssemblyReg<"%SP32">; 55 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
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D | WebAssemblyISelLowering.cpp | 51 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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/external/llvm-project/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrCall.td | 19 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in { 24 } // Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 27 let Uses = [SP32, SP64], isCall = 1 in { 78 } // Uses = [SP32,SP64], isCall = 1
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D | WebAssemblyRegisterInfo.td | 32 def SP32 : WebAssemblyReg<"%SP32">; 63 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
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D | WebAssemblyRegisterInfo.cpp | 47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs() 146 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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D | WebAssemblyFrameLowering.cpp | 129 : WebAssembly::SP32; in getSPReg()
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D | WebAssemblyISelLowering.cpp | 54 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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/external/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 458 def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 490 def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsRegisterInfo.td | 490 def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenRegisterInfo.inc | 2275 // SP32 Register Class... 2276 const MCPhysReg SP32[] = { 2280 // SP32 Bit set. 2710 { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 1, false }, 3993 { 32, 32, 32, VTLists+0 }, // SP32 6694 { // SP32 7185 {1, 1}, // SP32
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D | MipsGenAsmMatcher.inc | 1957 MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
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D | MipsGenInstrInfo.inc | 10827 SP32 = 220,
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