SPLAT (reference) in projects: external

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Searched refs:SPLAT (Results 1 – 25 of 29) sorted by relevance

/external/llvm/test/Transforms/CodeGenPrepare/X86/
D	x86-shuffle-sink.ll	`32 ; CHECK: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector 33 ; CHECK: shl <8 x i16> %lhs, [[SPLAT]] 72 ; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector 73 ; CHECK-SSE2: ashr <4 x i32> %lhs, [[SPLAT]] 93 ; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector 94 ; CHECK-SSE2: lshr <2 x i64> %lhs, [[SPLAT]]`
/external/llvm-project/llvm/test/Transforms/InstSimplify/
D	shufflevector.ll	31 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x i32> [[X:%.]], <4 x i32> undef, <4 x i32> zero… 32 ; CHECK-NEXT: ret <4 x i32> [[SPLAT]] 41 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x i32> [[X:%.]], <4 x i32> undef, <4 x i32> zero… 42 ; CHECK-NEXT: ret <4 x i32> [[SPLAT]] 51 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x i32> [[X:%.]], <4 x i32> [[Y:%.]], <4 x i32> … 52 ; CHECK-NEXT: ret <4 x i32> [[SPLAT]] 61 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x i32> [[X:%.]], <4 x i32> undef, <4 x i32> zero… 62 ; CHECK-NEXT: ret <4 x i32> [[SPLAT]] 71 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zero… 72 ; CHECK-NEXT: ret <4 x i32> [[SPLAT]] [all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
D	vscale_extractelement.ll	62 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef,… 63 ; CHECK-NEXT: [[R:%.]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 1 75 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef,… 76 ; CHECK-NEXT: [[R:%.]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 4 88 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef,… 89 ; CHECK-NEXT: [[R:%.]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 -1 102 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef,… 103 ; CHECK-NEXT: [[R:%.]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 [[IDX:%.*]]
D	insert-extract-shuffle.ll	431 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <… 432 ; CHECK-NEXT: ret <4 x float> [[SPLAT]] 442 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <3 x double> [[TMP1]], <3 x double> undef, <3 x i32>… 443 ; CHECK-NEXT: ret <3 x double> [[SPLAT]] 453 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> undef, <5 x i32> <i32 un… 454 ; CHECK-NEXT: ret <5 x i7> [[SPLAT]] 467 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i3… 468 ; CHECK-NEXT: ret <4 x float> [[SPLAT]] 481 ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i3… 482 ; CHECK-NEXT: ret <4 x float> [[SPLAT]] [all …]
D	vscale_insertelement.ll	`92 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef,… 93 ; CHECK-NEXT: [[I1:%.]] = insertelement <vscale x 4 x i32> [[SPLAT]], i32 undef, i8 -128`
D	vec_shuffle.ll	911 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <2 x i32> [[X:%.]], <2 x i32> undef, <2 x i32> zero… 912 ; CHECK-NEXT: [[R:%.]] = urem <2 x i32> <i32 42, i32 42>, [[SPLAT]] 933 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <2 x i32> [[X:%.]], <2 x i32> undef, <2 x i32> zero… 934 ; CHECK-NEXT: [[R:%.]] = srem <2 x i32> <i32 42, i32 42>, [[SPLAT]] 955 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <2 x i32> [[X:%.]], <2 x i32> undef, <2 x i32> zero… 956 ; CHECK-NEXT: [[R:%.]] = udiv <2 x i32> <i32 42, i32 42>, [[SPLAT]] 977 ; CHECK-NEXT: [[SPLAT:%.]] = shufflevector <2 x i32> [[X:%.]], <2 x i32> undef, <2 x i32> zero… 978 ; CHECK-NEXT: [[R:%.]] = sdiv <2 x i32> <i32 42, i32 42>, [[SPLAT]]
/external/llvm-project/mlir/test/mlir-cpu-runner/
D	utils.mlir	`4 …nalg_test_lib_dir/libmlir_runner_utils%shlibext \| FileCheck %s --check-prefix=PRINT-VECTOR-SPLAT-2D 70 // PRINT-VECTOR-SPLAT-2D: Memref base@ = {{.*}} rank = 2 offset = 0 sizes = [1, 1] strides = [1, 1]… 71 // PRINT-VECTOR-SPLAT-2D-NEXT: [((10, 10, 10, 10), (10, 10, 10, 10), (10, 10, 10, 10), (10, 1…`
/external/llvm/test/Transforms/LoopVectorize/
D	induction.ll	`498 ; IND: %[[SPLAT:.]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroinitiali… 499 ; IND: %[[START:.]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 42> 510 ; UNROLL: %[[SPLAT:.]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroiniti… 511 ; UNROLL: %[[START:.]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 42>`
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
D	induction.ll	706 ; CHECK: %[[SPLAT:.]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroinit… 707 ; CHECK: %[[START:.]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 1> 725 ; IND: %[[SPLAT:.]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroinitia… 726 ; IND: %[[START:.]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 1> 743 ; UNROLL: %[[SPLAT:.]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroini… 744 ; UNROLL: %[[START:.]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 1>
D	intrinsic.ll	`1381 …lvm.fshl.v4i32(<4 x i32> [[WIDE_LOADX:%.]], <4 x i32> [[WIDE_LOADY:%.]], <4 x i32> [[SPLAT:%.]]) 1407 …lvm.fshr.v4i32(<4 x i32> [[WIDE_LOADX:%.]], <4 x i32> [[WIDE_LOADY:%.]], <4 x i32> [[SPLAT:%.]])`
/external/llvm/lib/Target/SystemZ/
D	SystemZISelLowering.h	`179 SPLAT, enumerator`
D	SystemZOperators.td	`219 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;`
/external/llvm-project/llvm/lib/Target/SystemZ/
D	SystemZISelLowering.h	`184 SPLAT, enumerator`
D	SystemZOperators.td	`312 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;`
D	SystemZISelLowering.cpp	`4382 if (SystemZISD::SPLAT == ShuffleOp.getOpcode() && in getVPermMask() 5163 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0), in lowerVECTOR_SHUFFLE() 5608 OPCODE(SPLAT); in getTargetNodeName() 5716 else if ((Opcode == ISD::VECTOR_SHUFFLE \|\| Opcode == SystemZISD::SPLAT) && in combineExtract()`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
D	SystemZISelLowering.h	`183 SPLAT, enumerator`
D	SystemZOperators.td	`307 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;`
D	SystemZISelLowering.cpp	`4330 if (SystemZISD::SPLAT == ShuffleOp.getOpcode() && in getVPermMask() 4934 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0), in lowerVECTOR_SHUFFLE() 5352 OPCODE(SPLAT); in getTargetNodeName() 5460 else if ((Opcode == ISD::VECTOR_SHUFFLE \|\| Opcode == SystemZISD::SPLAT) && in combineExtract()`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
D	P9InstrResources.td	`1369 (instregex "EVLHH(E\|OS\|OU)SPLAT(X)?$"), 1372 (instregex "EVLW(H\|W)SPLAT(X)?$"),`
/external/llvm-project/llvm/lib/Target/PowerPC/
D	P9InstrResources.td	`1370 (instregex "EVLHH(E\|OS\|OU)SPLAT(X)?$"), 1373 (instregex "EVLW(H\|W)SPLAT(X)?$"),`
/external/llvm-project/llvm/test/CodeGen/AArch64/
D	sve2-int-mul.ll	`8 ; MUL with SPLAT`
/external/llvm-project/mlir/test/Conversion/VectorToSCF/
D	vector-to-loops.mlir	`213 // FULL-UNROLL: %[[SPLAT:.*]] = constant dense<7.000000e+00> : vector<15xf32>`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
D	MipsScheduleP5600.td	`345 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT\|SPLATI)_[BHWD]$")>;`
/external/llvm-project/llvm/lib/Target/Mips/
D	MipsScheduleP5600.td	`346 def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT\|SPLATI)_[BHWD]$")>;`
/external/llvm-project/mlir/test/Conversion/StandardToLLVM/
D	convert-to-llvmir.mlir	`865 // CHECK-NEXT: %[[SPLAT:[0-9]+]] = llvm.shufflevector %[[V]], %[[UNDEF]] [0 : i32, 0 : i32, 0 : i32… 866 // CHECK-NEXT: %[[SCALE:[0-9]+]] = llvm.fmul %[[A]], %[[SPLAT]] : !llvm.vec<4 x float>`

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