/external/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> { 113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr), 124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> { 132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr), 343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), [all …]
|
D | ARMRegisterInfo.td | 272 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 273 let AltOrders = [(add (decimate SPR, 2), SPR), 274 (add (decimate SPR, 4), 275 (decimate SPR, 2), 276 (decimate (rotl SPR, 1), 4), 277 (decimate (rotl SPR, 1), 2))]; 283 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 303 // 32-bit SPR subregs). 320 // Subset of QPR that have 32-bit SPR subregs.
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 149 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 151 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 171 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 173 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 377 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 379 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 402 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 404 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 427 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 429 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, [all …]
|
D | ARMRegisterInfo.td | 370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 371 let AltOrders = [(add (decimate SPR, 2), SPR), 372 (add (decimate SPR, 4), 373 (decimate SPR, 2), 374 (decimate (rotl SPR, 1), 4), 375 (decimate (rotl SPR, 1), 2))]; 383 let AltOrders = [(add (decimate HPR, 2), SPR), 394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 424 // 32-bit SPR subregs). [all …]
|
D | ARMRegisterBanks.td | 13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
|
/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, [all …]
|
D | ARMInstrCDE.td | 487 def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>; 550 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)), 551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>; 557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)), 558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>; 559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n), 561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>; 568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m), 570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m), 572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n), [all …]
|
D | ARMRegisterInfo.td | 381 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 382 let AltOrders = [(add (decimate SPR, 2), SPR), 383 (add (decimate SPR, 4), 384 (decimate SPR, 2), 385 (decimate (rotl SPR, 1), 4), 386 (decimate (rotl SPR, 1), 2))]; 394 let AltOrders = [(add (decimate HPR, 2), SPR), 405 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 430 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 435 // 32-bit SPR subregs). [all …]
|
D | ARMRegisterBanks.td | 13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 47 // SPR - One of the 32-bit special-purpose registers 48 class SPR<bits<10> num, string n> : PPCReg<n> { 218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 238 // (which really is SPR register 1); this is the only bit interesting to a [all …]
|
D | PPCInstrFormats.td | 1560 bits<10> SPR; 1563 let Inst{11} = SPR{4}; 1564 let Inst{12} = SPR{3}; 1565 let Inst{13} = SPR{2}; 1566 let Inst{14} = SPR{1}; 1567 let Inst{15} = SPR{0}; 1568 let Inst{16} = SPR{9}; 1569 let Inst{17} = SPR{8}; 1570 let Inst{18} = SPR{7}; 1571 let Inst{19} = SPR{6}; [all …]
|
/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 51 // SPR - One of the 32-bit special-purpose registers 52 class SPR<bits<10> num, string n> : PPCReg<n> { 247 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 252 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 256 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 262 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 264 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 267 // (which really is SPR register 1); this is the only bit interesting to a [all …]
|
D | PPCInstrFormats.td | 1564 bits<10> SPR; 1567 let Inst{11} = SPR{4}; 1568 let Inst{12} = SPR{3}; 1569 let Inst{13} = SPR{2}; 1570 let Inst{14} = SPR{1}; 1571 let Inst{15} = SPR{0}; 1572 let Inst{16} = SPR{9}; 1573 let Inst{17} = SPR{8}; 1574 let Inst{18} = SPR{7}; 1575 let Inst{19} = SPR{6}; [all …]
|
/external/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.td | 42 // SPR - One of the 32-bit special-purpose registers 43 class SPR<bits<10> num, string n> : PPCReg<n> { 205 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 207 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 210 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 211 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 214 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 217 // (which really is SPR register 1); this is the only bit interesting to a 219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
|
D | PPCInstrFormats.td | 1345 bits<10> SPR; 1348 let Inst{11} = SPR{4}; 1349 let Inst{12} = SPR{3}; 1350 let Inst{13} = SPR{2}; 1351 let Inst{14} = SPR{1}; 1352 let Inst{15} = SPR{0}; 1353 let Inst{16} = SPR{9}; 1354 let Inst{17} = SPR{8}; 1355 let Inst{18} = SPR{7}; 1356 let Inst{19} = SPR{6}; [all …]
|
/external/llvm-project/llvm/test/CodeGen/ARM/ |
D | inlineasm-X-allocation.ll | 5 ; Using this mechanism, we want to test toggling allocating GPR or SPR registers
|
/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
D | arm-select-copy_to_regclass-of-fptosi.mir | 8 # G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
|
/external/llvm-project/llvm/lib/Target/X86/ |
D | X86PartialReduction.cpp | 186 auto SPR = matchSelectPattern(SI, LHS, RHS); in trySADReplacement() local 187 if (SPR.Flavor != SPF_ABS) in trySADReplacement()
|
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenDAGISel.inc | 10821 …:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (ARMvdup:{ *:[v4f32] } SPR:{ *:[f32] }:$v2), 0… 10822 …CMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$v2, rG… 10836 …:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (ARMvdup:{ *:[v4f32] } SPR:{ *:[f32] }:$v2), 1… 10837 …CMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$v2, rG… 10851 …:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (ARMvdup:{ *:[v4f32] } SPR:{ *:[f32] }:$v2), 1… 10852 …CMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$v2, rG… 10866 …:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (ARMvdup:{ *:[v4f32] } SPR:{ *:[f32] }:$v2), 1… 10867 …CMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$v2, rG… 10881 …:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (ARMvdup:{ *:[v4f32] } SPR:{ *:[f32] }:$v2), 1… 10882 …CMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$v2, rG… [all …]
|
D | ARMGenInstrInfo.inc | 14854 SPR = 325, 19528 OpTypes::SPR, OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 19769 OpTypes::SPR, OpTypes::vfp_f32imm, OpTypes::i32imm, OpTypes::i32imm, 21023 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21053 OpTypes::SPR, OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21205 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21208 OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21210 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21213 OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21224 OpTypes::SPR, OpTypes::DPR, [all …]
|
/external/llvm-project/llvm/lib/Analysis/ |
D | LazyValueInfo.cpp | 825 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local 828 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect() 831 switch (SPR.Flavor) { in solveBlockValueSelect() 849 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect() 858 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
D | LazyValueInfo.cpp | 895 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local 898 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect() 901 switch (SPR.Flavor) { in solveBlockValueSelect() 918 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect() 929 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()
|
/external/llvm/lib/Transforms/InstCombine/ |
D | InstCombineSelect.cpp | 1105 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local 1106 auto SPF = SPR.Flavor; in visitSelectInst() 1112 CmpInst::Predicate Pred = getCmpPredicateForMinMax(SPF, SPR.Ordered); in visitSelectInst()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
D | InstCombineSelect.cpp | 1006 SelectPatternResult SPR = matchSelectPattern(&Sel, LHS, RHS); in canonicalizeMinMaxWithConstant() local 1007 if (!SelectPatternResult::isMinOrMax(SPR.Flavor)) in canonicalizeMinMaxWithConstant() 1011 ICmpInst::Predicate CanonicalPred = getMinMaxPred(SPR.Flavor); in canonicalizeMinMaxWithConstant() 2541 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local 2542 auto SPF = SPR.Flavor; in visitSelectInst() 2569 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
|
/external/llvm/lib/Analysis/ |
D | LazyValueInfo.cpp | 914 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local 917 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect() 919 switch (SPR.Flavor) { in solveBlockValueSelect()
|