Searched refs:SPSR (Results 1 – 23 of 23) sorted by relevance
| /external/arm-trusted-firmware/docs/plat/ |
| D | intel-agilex.rst | 78 INFO: SPSR = 0x3cd
86 INFO: SPSR = 0x3c9
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| D | intel-stratix10.rst | 85 INFO: SPSR = 0x3cd
93 INFO: SPSR = 0x3c9
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| D | poplar.rst | 128 INFO: SPSR = 0x3c5
139 INFO: SPSR = 0x3cd
146 INFO: SPSR = 0x3c9
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| D | rz-g2.rst | 213 INFO: SPSR = 0x3cd
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| D | rcar-gen3.rst | 244 INFO: SPSR = 0x3cd
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| /external/arm-trusted-firmware/docs/ |
| D | change-log-upcoming.rst | 82 - Example: "Refactor SPSR initialisation code"
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| D | change-log.rst | 1253 variant 4 by disabling speculative loads/stores (SPSR.SSBS bit) by default.
1375 - Refactor SPSR initialisation code
3461 based on the SPSR value provided by the BL2 platform code (or otherwise
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 212 case SPSR: in GetName()
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| D | instructions-aarch32.h | 768 enum SpecialRegisterType { APSR = 0, CPSR = 0, SPSR = 1 }; enumerator
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| /external/arm-trusted-firmware/docs/getting_started/ |
| D | psci-lib-integration-guide.rst | 108 #. The PSCI library provides appropriate LR and SPSR values (entrypoint
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 166 def SPSR : ARMReg<2, "spsr">;
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| D | ARMInstrThumb2.td | 4027 // A/R class can only move from CPSR or SPSR.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 185 def SPSR : ARMReg<2, "spsr">;
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| D | ARMInstrThumb2.td | 4261 // A/R class can only move from CPSR or SPSR.
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 185 def SPSR : ARMReg<2, "spsr">;
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| D | ARMInstrThumb2.td | 4330 // A/R class can only move from CPSR or SPSR.
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| /external/arm-trusted-firmware/docs/design/ |
| D | firmware-design.rst | 435 of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
448 memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
450 image. The ``SPSR`` is determined as specified in Section 5.13 of the
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 36 SPSR = 16,
1493 { ARM::SPSR },
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| D | ARMGenAsmMatcher.inc | 5581 MCK_SPSR, // register class 'SPSR'
9174 case ARM::SPSR: OpKind = MCK_SPSR; break;
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| /external/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 12682 CPSRWriteByInstr(SPSR[], '1111', TRUE); in EmulateSUBSPcLrEtc()
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| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x10.txt | 826 Instruction 768 S:0xC000CE64 0xF3FF8800 5 MRS r8,SPSR false
1011 Instruction 943 S:0xC000CE64 0xF3FF8800 5 MRS r8,SPSR false
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| D | etmv3_0x11.txt | 7521 Instruction 7276 S:0xC000CE64 0xF3FF8800 5 MRS r8,SPSR false
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| D | ptmv1_0x13.txt | 5315 Instruction 5117 S:0xC000CE64 0xF3FF8800 0 MRS r8,SPSR false
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