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Searched refs:SReg (Results 1 – 25 of 40) sorted by relevance

12

/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
376 if (!isRegUsed(SReg)) { in scavengeRegister()
377 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); in scavengeRegister()
378 return SReg; in scavengeRegister()
420 Scavenged[SI].Reg = SReg; in scavengeRegister()
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
429 TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) + in scavengeRegister()
433 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex, in scavengeRegister()
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex, in scavengeRegister()
454 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << in scavengeRegister()
[all …]
/external/llvm-project/llvm/lib/CodeGen/
DRegisterScavenging.cpp541 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
544 if (!isRegUsed(SReg)) { in scavengeRegister()
545 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
546 return SReg; in scavengeRegister()
552 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
556 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
558 return SReg; in scavengeRegister()
649 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
651 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
653 return SReg; in scavengeVReg()
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DLivePhysRegs.cpp263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) { in addLiveIns()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterScavenging.cpp560 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
563 if (!isRegUsed(SReg)) { in scavengeRegister()
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
565 return SReg; in scavengeRegister()
571 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); in scavengeRegister()
575 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
577 return SReg; in scavengeRegister()
668 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
670 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
672 return SReg; in scavengeVReg()
[all …]
DLivePhysRegs.cpp263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) { in addLiveIns()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp103 unsigned getDPRLaneFromSPR(unsigned SReg);
118 unsigned getPrefSPRLane(unsigned SReg);
147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
157 if (!TRI->isVirtualRegister(SReg)) in getPrefSPRLane()
158 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
160 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
162 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
169 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
154 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
155 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
165 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
154 if (!Register::isVirtualRegister(SReg)) in getPrefSPRLane()
155 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
165 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIPreEmitPeephole.cpp107 Register SReg; in optimizeVccBranch() local
109 SReg = Op2.getReg(); in optimizeVccBranch()
113 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
115 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
117 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
156 if (SReg == ExecReg) { in optimizeVccBranch()
DSIShrinkInstructions.cpp768 Register SReg = Src2->getReg(); in runOnMachineFunction() local
769 if (SReg.isVirtual()) { in runOnMachineFunction()
770 MRI.setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
773 if (SReg != VCCReg) in runOnMachineFunction()
DSIInstrInfo.cpp1045 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1046 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
1053 .addReg(SReg); in insertVectorSelect()
1058 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1060 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1068 .addReg(SReg); in insertVectorSelect()
1072 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
1074 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
1082 .addReg(SReg); in insertVectorSelect()
1088 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp382 unsigned SReg = AMDGPU::NoRegister; in optimizeVccBranch() local
384 SReg = Op2.getReg(); in optimizeVccBranch()
388 if (M->definesRegister(SReg, TRI)) in optimizeVccBranch()
390 if (M->modifiesRegister(SReg, TRI)) in optimizeVccBranch()
392 ReadsSreg |= M->readsRegister(SReg, TRI); in optimizeVccBranch()
412 if (SReg == ExecReg) { in optimizeVccBranch()
DSIShrinkInstructions.cpp746 Register SReg = Src2->getReg(); in runOnMachineFunction() local
747 if (Register::isVirtualRegister(SReg)) { in runOnMachineFunction()
748 MRI.setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
751 if (SReg != VCCReg) in runOnMachineFunction()
DSIInstrInfo.cpp834 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
835 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
842 .addReg(SReg); in insertVectorSelect()
847 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
849 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
857 .addReg(SReg); in insertVectorSelect()
861 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
863 : AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
871 .addReg(SReg); in insertVectorSelect()
877 Register SReg = MRI.createVirtualRegister(BoolXExecRC); in insertVectorSelect() local
[all …]
/external/llvm/include/llvm/CodeGen/
DVirtRegMap.h138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg() argument
139 Virt2SplitMap[virtReg] = SReg; in setIsSplitFromReg()
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp352 unsigned SReg = Src2->getReg(); in runOnMachineFunction() local
353 if (TargetRegisterInfo::isVirtualRegister(SReg)) { in runOnMachineFunction()
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
357 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DVirtRegMap.h135 void setIsSplitFromReg(Register virtReg, unsigned SReg) { in setIsSplitFromReg() argument
136 Virt2SplitMap[virtReg.id()] = SReg; in setIsSplitFromReg()
/external/llvm-project/llvm/include/llvm/CodeGen/
DVirtRegMap.h134 void setIsSplitFromReg(Register virtReg, unsigned SReg) { in setIsSplitFromReg() argument
135 Virt2SplitMap[virtReg.id()] = SReg; in setIsSplitFromReg()
/external/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h992 ParamVarRegion(const Expr *OE, unsigned Idx, const MemRegion *SReg) in ParamVarRegion() argument
993 : VarRegion(SReg, ParamVarRegionKind), OriginExpr(OE), Index(Idx) { in ParamVarRegion()
994 assert(!cast<StackSpaceRegion>(SReg)->getStackFrame()->inTopFrame()); in ParamVarRegion()
998 unsigned Idx, const MemRegion *SReg);
1217 const SubRegion *SReg) in CXXBaseObjectRegion() argument
1218 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) { in CXXBaseObjectRegion()
1223 bool IsVirtual, const MemRegion *SReg);
1254 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) in CXXDerivedObjectRegion() argument
1255 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) { in CXXDerivedObjectRegion()
1260 assert(SReg->getSymbolicBase() && in CXXDerivedObjectRegion()
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/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3387 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
3396 if (DReg == SReg) { in expandRotation()
3404 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
3409 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3436 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
3437 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3452 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
3465 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
3470 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
3480 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
[all …]
/external/llvm-project/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp306 unsigned Idx, const MemRegion *SReg) { in ProfileRegion() argument
310 ID.AddPointer(SReg); in ProfileRegion()
394 const MemRegion *SReg) { in ProfileRegion() argument
397 ID.AddPointer(SReg); in ProfileRegion()
406 const MemRegion *SReg) { in ProfileRegion() argument
408 ID.AddPointer(SReg); in ProfileRegion()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp1126 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
1130 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) in eliminateFrameIndex()
1135 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
1161 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4861 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4869 if (DReg == SReg) { in expandRotation()
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4908 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4924 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4751 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4759 if (DReg == SReg) { in expandRotation()
4767 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4798 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4814 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4826 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4831 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4840 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
[all …]
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h1080 const MemRegion *SReg) in CXXBaseObjectRegion() argument
1081 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) {} in CXXBaseObjectRegion()
1084 bool IsVirtual, const MemRegion *SReg);

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