Searched refs:SSBS (Results 1 – 22 of 22) sorted by relevance
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | armv8.5a-ssbs.s | 12 mrs x2, SSBS
18 msr SSBS, x3
19 msr SSBS, #1
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| D | armv8.5a-ssbs-error.s | 5 msr SSBS, #2
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| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.5a-ssbs.txt | 10 # CHECK: msr SSBS, #1
11 # CHECK: msr SSBS, x3
12 # CHECK: mrs x2, SSBS
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| /external/arm-trusted-firmware/docs/ |
| D | global_substitutions.txt | 50 .. |SSBS| replace:: :term:`SSBS`
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| D | glossary.rst | 167 SSBS
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| D | change-log.rst | 1144 - Neoverse Zeus: Apply the MSR SSBS instruction
1252 - Speculative Store Bypass Safe (SSBS): Further enhance protection against Spectre
1253 variant 4 by disabling speculative loads/stores (SPSR.SSBS bit) by default.
1698 - Use Speculation Store Bypass Safe (SSBS) functionality where available
1821 - Incorrect check for SSBS feature detection
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| /external/arm-trusted-firmware/lib/cpus/aarch64/ |
| D | cortex_matterhorn.S | 51 msr SSBS, xzr
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| D | cortex_klein.S | 51 msr SSBS, xzr
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| D | neoverse_v1.S | 53 msr SSBS, xzr
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| D | neoverse_n2.S | 33 msr SSBS, xzr
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| D | rainier.S | 38 msr SSBS, xzr
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| D | neoverse_n1.S | 74 msr SSBS, xzr
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSystemOperands.inc | 144 SSBS = 25,
936 SSBS = 55830,
1954 { "SSBS", 0x19, {AArch64::FeatureSSBS} }, // 6
1969 { "SSBS", 6 },
3000 { "SSBS", 0xDA16, true, true, {AArch64::FeatureSSBS} }, // 746
3532 { "SSBS", 746 },
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| /external/arm-trusted-firmware/include/arch/aarch64/ |
| D | arch.h | 1046 #define SSBS S3_3_C4_C2_6 macro
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 346 def : PState<"SSBS", 0b11001>;
1451 // V8.5a Spectre mitigation SSBS register
1454 def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
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| D | AArch64ISelDAGToDAG.cpp | 2811 if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO || Reg == AArch64PState::SSBS) { in tryWriteRegister()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 351 def : PState<"SSBS", 0b11001>;
1453 // V8.5a Spectre mitigation SSBS register
1456 def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
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| D | AArch64ISelDAGToDAG.cpp | 2993 if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO || Reg == AArch64PState::SSBS) { in tryWriteRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1737 pstate_field == AArch64PState::SSBS) && crm > 1) in DecodeSystemPStateInstruction()
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| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1773 pstate_field == AArch64PState::SSBS) && crm > 1) in DecodeSystemPStateInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1014 SysReg.PStateField == AArch64PState::SSBS); in isSystemPStateFieldWithImm0_1()
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| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1053 SysReg.PStateField == AArch64PState::SSBS); in isSystemPStateFieldWithImm0_1()
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