1/* 2 * Copyright (c) 2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_matterhorn.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* ---------------------------------------------------- 25 * HW will do the cache maintenance while powering down 26 * ---------------------------------------------------- 27 */ 28func cortex_matterhorn_core_pwr_dwn 29 /* --------------------------------------------------- 30 * Enable CPU power down bit in power control register 31 * --------------------------------------------------- 32 */ 33 mrs x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1 34 orr x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 35 msr CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_matterhorn_core_pwr_dwn 39 40 /* 41 * Errata printing function for Cortex Matterhorn. Must follow AAPCS. 42 */ 43#if REPORT_ERRATA 44func cortex_matterhorn_errata_report 45 ret 46endfunc cortex_matterhorn_errata_report 47#endif 48 49func cortex_matterhorn_reset_func 50 /* Disable speculative loads */ 51 msr SSBS, xzr 52 isb 53 ret 54endfunc cortex_matterhorn_reset_func 55 56 /* --------------------------------------------- 57 * This function provides Cortex-Matterhorn specific 58 * register information for crash reporting. 59 * It needs to return with x6 pointing to 60 * a list of register names in ascii and 61 * x8 - x15 having values of registers to be 62 * reported. 63 * --------------------------------------------- 64 */ 65.section .rodata.cortex_matterhorn_regs, "aS" 66cortex_matterhorn_regs: /* The ascii list of register names to be reported */ 67 .asciz "cpuectlr_el1", "" 68 69func cortex_matterhorn_cpu_reg_dump 70 adr x6, cortex_matterhorn_regs 71 mrs x8, CORTEX_MATTERHORN_CPUECTLR_EL1 72 ret 73endfunc cortex_matterhorn_cpu_reg_dump 74 75declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \ 76 cortex_matterhorn_reset_func, \ 77 cortex_matterhorn_core_pwr_dwn 78