| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | stack-coloring-vararg.mir | 140 STFD %8, 32, %stack.2 :: (store 8)
141 STFD %9, 40, %stack.2 :: (store 8)
142 STFD %10, 48, %stack.2 :: (store 8)
143 STFD %11, 56, %stack.2 :: (store 8)
144 STFD %12, 64, %stack.2 :: (store 8)
145 STFD %13, 72, %stack.2 :: (store 8)
146 STFD %14, 80, %stack.2 :: (store 8)
147 STFD %15, 88, %stack.2 :: (store 8)
|
| D | aix-csr.ll | 167 ; MIR64-DAG: STFD killed $f14, 256, $x1 :: (store 8 into %fixed-stack.3, align 16)
168 ; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store 8 into %fixed-stack.2)
169 ; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store 8 into %fixed-stack.1)
170 ; MIR64-DAG: STFD killed $f31, 392, $x1 :: (store 8 into %fixed-stack.0)
197 ; MIR32-DAG: STFD killed $f14, 144, $r1 :: (store 8 into %fixed-stack.3, align 16)
198 ; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store 8 into %fixed-stack.2)
199 ; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store 8 into %fixed-stack.1)
200 ; MIR32-DAG: STFD killed $f31, 280, $r1 :: (store 8 into %fixed-stack.0)
|
| D | aix-csr-vector.ll | 155 ; MIR32-DAG: STFD killed $f14, 304, $r1 :: (store 8 into %fixed-stack.5, align 16)
156 ; MIR32-DAG: STFD killed $f21, 360, $r1 :: (store 8 into %fixed-stack.4)
157 ; MIR32-DAG: STFD killed $f31, 440, $r1 :: (store 8 into %fixed-stack.3)
221 ; MIR64-DAG: STFD killed $f14, 400, $x1 :: (store 8 into %fixed-stack.5, align 16)
222 ; MIR64-DAG: STFD killed $f21, 456, $x1 :: (store 8 into %fixed-stack.4)
223 ; MIR64-DAG: STFD killed $f31, 536, $x1 :: (store 8 into %fixed-stack.3)
|
| D | aix-cc-abi.ll | 453 ; 32BIT-DAG: STFD renamable $f1, 56, $r1 :: (store 8)
454 ; 32BIT-DAG: STFD renamable $f1, 64, $r1 :: (store 8)
455 ; 32BIT-DAG: STFD renamable $f1, 72, $r1 :: (store 8)
456 ; 32BIT-DAG: STFD renamable $f1, 80, $r1 :: (store 8)
457 ; 32BIT-DAG: STFD renamable $f1, 88, $r1 :: (store 8)
458 ; 32BIT-DAG: STFD renamable $f1, 96, $r1 :: (store 8)
459 ; 32BIT-DAG: STFD renamable $f1, 104, $r1 :: (store 8)
460 ; 32BIT-DAG: STFD renamable $f1, 112, $r1 :: (store 8)
461 ; 32BIT-DAG: STFD renamable $f1, 120, $r1 :: (store 8)
510 ; 64BIT-DAG: STFD renamable $f1, 112, $x1 :: (store 8)
[all …]
|
| D | fusion-load-store.ll | 139 ; CHECK: SU([[SU0]]): STFD renamable $f[[REG:[0-9]+]], 8
140 ; CHECK: SU([[SU1]]): STFD renamable $f[[REG]], 16
141 ; CHECK: SU([[SU2]]): STFD renamable $f[[REG]], 24
142 ; CHECK: SU([[SU3]]): STFD renamable $f[[REG]], 32
|
| D | fold-frame-offset-using-rr.mir | 165 STFD killed $f1, -8, killed $x4
|
| D | convert-rr-to-ri-instrs.mir | 5956 ; CHECK: STFD %1, 876, %0
5963 ; CHECK: STFD %1, -873, %0
|
| /external/llvm-project/lld/ELF/Arch/ |
| D | PPCInsns.def | 24 PCREL_OPT(STFD, PSTFD, OPC_AND_RST);
|
| D | PPC64.cpp | 90 STFD = 0xd8000000, enumerator
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 159 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
166 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
173 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
|
| D | PPCPreEmitPeephole.cpp | 82 case PPC::STFD: in hasPCRelativeForm()
|
| D | PPCFastISel.cpp | 654 Opc = Subtarget->hasSPE() ? PPC::EVSTDD : PPC::STFD; in PPCEmitStore()
668 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD; in PPCEmitStore()
718 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break; in PPCEmitStore()
|
| D | PPCInstrInfo.cpp | 2331 case PPC::STFD: in isClusterableLdStOpcPair()
2482 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
3689 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
3830 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
|
| D | PPCRegisterInfo.cpp | 106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 649 Opc = PPC::STFD; in PPCEmitStore()
663 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD; in PPCEmitStore()
712 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break; in PPCEmitStore()
|
| D | PPCInstrInfo.cpp | 300 case PPC::STFD: in isStoreToStackSlot()
979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
|
| D | PPCRegisterInfo.cpp | 71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
|
| D | PPCISelDAGToDAG.cpp | 4294 case PPC::STFD: in PeepholePPC64()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 653 Opc = PPCSubTarget->hasSPE() ? PPC::EVSTDD : PPC::STFD; in PPCEmitStore()
667 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD; in PPCEmitStore()
717 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break; in PPCEmitStore()
|
| D | PPCInstrInfo.cpp | 2067 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
2406 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, in getStoreOpcodesForSpillArray()
2411 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, in getStoreOpcodesForSpillArray()
3256 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
3397 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
|
| D | PPCRegisterInfo.cpp | 91 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
|
| D | PPCISelDAGToDAG.cpp | 6476 case PPC::STFD: in PeepholePPC64()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenMCCodeEmitter.inc | 1586 UINT64_C(3623878656), // STFD
2705 case PPC::STFD:
7996 CEFBS_None, // STFD = 1573
|
| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 1083 58739441U, // STFD
2605 0U, // STFD
|
| D | PPCGenDisassemblerTables.inc | 1556 /* 6417 */ MCD_OPC_Decode, 167, 8, 84, // Opcode: STFD
|