| /external/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 75 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
92 case Mips::ST_W: in getLoadStoreOffsetAlign()
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| D | MipsSEInstrInfo.cpp | 215 Opc = Mips::ST_W; in storeRegToStack()
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| D | MipsMSAInstrInfo.td | 3465 def ST_W: ST_W_ENC, ST_W_DESC;
3533 (ST_W MSA128W:$ws, addrimm10:$addr)>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 75 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
135 case Mips::ST_W: in getLoadStoreOffsetAlign()
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| D | MipsInstructionSelector.cpp | 239 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
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| D | MipsSEInstrInfo.cpp | 279 Opc = Mips::ST_W; in storeRegToStack()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 75 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
135 case Mips::ST_W: in getLoadStoreOffsetAlign()
|
| D | MipsInstructionSelector.cpp | 245 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
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| D | MipsSEInstrInfo.cpp | 279 Opc = Mips::ST_W; in storeRegToStack()
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| D | MipsMSAInstrInfo.td | 3525 def ST_W: ST_W_ENC, ST_W_DESC;
3593 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | floating_point_vec_arithmetic_operations.mir | 36 ; P5600: ST_W [[FADD_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
96 ; P5600: ST_W [[FSUB_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
156 ; P5600: ST_W [[FMUL_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
216 ; P5600: ST_W [[FDIV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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| D | load_store_vec.mir | 76 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
124 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
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| D | fsqrt_vec.mir | 25 ; P5600: ST_W [[FSQRT_W]], [[COPY1]], 0 :: (store 16 into %ir.c)
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| D | fabs_vec.mir | 25 ; P5600: ST_W [[FABS_W]], [[COPY1]], 0 :: (store 16 into %ir.c)
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| D | rem_and_div_vec.mir | 104 ; P5600: ST_W [[DIV_S_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
224 ; P5600: ST_W [[MOD_S_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
344 ; P5600: ST_W [[DIV_U_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
464 ; P5600: ST_W [[MOD_U_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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| D | sub_vec.mir | 89 ; P5600: ST_W [[SUBV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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| D | mul_vec.mir | 89 ; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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| D | add_vec.mir | 89 ; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
|
| /external/webp/src/dsp/ |
| D | msa_macro.h | 68 #define ST_W(RTYPE, in, pdst) *((RTYPE*)(pdst)) = in macro
69 #define ST_UW(...) ST_W(v4u32, __VA_ARGS__)
70 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
325 ST_W(RTYPE, in0, pdst); \
326 ST_W(RTYPE, in1, pdst + stride); \
333 ST_W(RTYPE, in2, pdst + 2 * stride); \
|
| /external/libvpx/libvpx/vp8/common/mips/msa/ |
| D | vp8_macros_msa.h | 39 #define ST_W(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in) macro
40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
|
| /external/libaom/libaom/aom_dsp/mips/ |
| D | macros_msa.h | 39 #define ST_W(RTYPE, in, pdst) *((RTYPE *)(pdst)) = (in) macro
40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1495 case Mips::ST_W: in DecodeMSA128Mem()
|
| /external/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1738 case Mips::ST_W: in DecodeMSA128Mem()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1738 case Mips::ST_W: in DecodeMSA128Mem()
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1614 58745378U, // ST_W
3403 0U, // ST_W
|