| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable() argument
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
75 if (I->getSUnit() == SU) in isResourceAvailable()
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { in reserveResources() argument
86 if (!SU) { in reserveResources()
94 if (!isResourceAvailable(SU)) { in reserveResources()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 97 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { in isResourceAvailable() argument
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
127 if (hasDependence(Packet[i], SU, QII)) in isResourceAvailable()
131 if (hasDependence(SU, Packet[i], QII)) in isResourceAvailable()
138 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { in reserveResources() argument
141 if (!SU) { in reserveResources()
149 if (!isResourceAvailable(SU, IsTop) || in reserveResources()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 97 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { in isResourceAvailable() argument
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
127 if (hasDependence(Packet[i], SU, QII)) in isResourceAvailable()
131 if (hasDependence(SU, Packet[i], QII)) in isResourceAvailable()
138 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { in reserveResources() argument
141 if (!SU) { in reserveResources()
149 if (!isResourceAvailable(SU, IsTop) || in reserveResources()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
69 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
142 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
144 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
151 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
153 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
168 SUnit *SU = &(*SUnits)[i]; in initNodes() local
169 initNumRegDefsLeft(SU); in initNodes()
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| D | ScheduleDAGRRList.cpp | 212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
213 return Topo.IsReachable(SU, TargetSU); in IsReachable()
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
219 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued() argument
226 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
227 SU->addPred(D); in AddPredQueued()
233 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
234 Topo.AddPred(SU, D.getSUnit()); in AddPred()
235 SU->addPred(D); in AddPred()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
73 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
111 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
146 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
148 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
172 SUnit *SU = &(*SUnits)[i]; in initNodes() local
173 initNumRegDefsLeft(SU); in initNodes()
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| D | ScheduleDAGRRList.cpp | 212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
213 return Topo.IsReachable(SU, TargetSU); in IsReachable()
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
219 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued() argument
226 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
227 SU->addPred(D); in AddPredQueued()
233 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
234 Topo.AddPred(SU, D.getSUnit()); in AddPred()
235 SU->addPred(D); in AddPred()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
173 SUnit *SU = &(*SUnits)[i]; in initNodes() local
174 initNumRegDefsLeft(SU); in initNodes()
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| D | ScheduleDAGRRList.cpp | 186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
209 SU->removePred(D); in RemovePred()
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | fusion-load-store.ll | 2 ; scheduler will print "Cluster ld/st SU(x) - SU(y)" if SU(x) and SU(y) are fused.
13 ; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
14 ; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
15 ; CHECK: SU([[SU2]]): STD %[[REG:[0-9]+]]:g8rc, 24
16 ; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, 16
17 ; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, 8
18 ; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, 32
21 ; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
22 ; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
23 ; CHECK: SU([[SU0]]): STD renamable $x[[REG:[0-9]+]], 16
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNMinRegStrategy.cpp | 38 const SUnit *SU; member
42 : SU(SU_), Priority(Priority_) {} in Candidate()
51 bool isScheduled(const SUnit *SU) const { in isScheduled()
52 assert(!SU->isBoundaryNode()); in isScheduled()
53 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); in isScheduled()
56 void setIsScheduled(const SUnit *SU) { in setIsScheduled() argument
57 assert(!SU->isBoundaryNode()); in setIsScheduled()
58 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); in setIsScheduled()
61 unsigned getNumPreds(const SUnit *SU) const { in getNumPreds()
62 assert(!SU->isBoundaryNode()); in getNumPreds()
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| D | GCNILPSched.cpp | 24 SUnit *SU; member
27 : SU(SU_) {} in Candidate()
41 unsigned getNodePriority(const SUnit *SU) const;
48 void releasePredecessors(const SUnit* SU);
59 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
65 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
87 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const { in getNodePriority()
88 assert(SU->NodeNum < SUNumbers.size()); in getNodePriority()
89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNMinRegStrategy.cpp | 31 const SUnit *SU; member
35 : SU(SU_), Priority(Priority_) {} in Candidate()
44 bool isScheduled(const SUnit *SU) const { in isScheduled()
45 assert(!SU->isBoundaryNode()); in isScheduled()
46 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); in isScheduled()
49 void setIsScheduled(const SUnit *SU) { in setIsScheduled() argument
50 assert(!SU->isBoundaryNode()); in setIsScheduled()
51 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); in setIsScheduled()
54 unsigned getNumPreds(const SUnit *SU) const { in getNumPreds()
55 assert(!SU->isBoundaryNode()); in getNumPreds()
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| D | GCNILPSched.cpp | 24 SUnit *SU; member
27 : SU(SU_) {} in Candidate()
41 unsigned getNodePriority(const SUnit *SU) const;
48 void releasePredecessors(const SUnit* SU);
59 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
65 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
87 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const { in getNodePriority()
88 assert(SU->NodeNum < SUNumbers.size()); in getNodePriority()
89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | misched-fusion-crypto-eor.mir | 9 ; CHECK: SU(0): %0:fpr128 = AESErr undef $q0(tied-def 0), undef $q1
11 ; NOFUSE-NOT: SU({{.*}}): Ord
12 ; FUSEAES: SU(1): Ord Latency=0 Cluster
13 ; CHECK: SU(1): %1:fpr128 = AESMCrrTied %0:fpr128
17 ; CHECK: SU(2): %2:fpr128 = AESErr undef $q2(tied-def 0), undef $q3
19 ; NOFUSE-NOT: SU({{.*}}): Ord
20 ; FUSEAES: SU(3): Ord Latency=0 Cluster
21 ; CHECK: SU(3): dead %3:fpr128 = AESMCrr %2:fpr128
25 ; CHECK: SU(4): %4:fpr128 = AESErr %1:fpr128(tied-def 0), undef $q4
27 ; NOFUSE-NOT: SU({{.*}}): Ord
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| D | aarch64-stp-cluster.ll | 7 ; CHECK:Cluster ld/st SU(3) - SU(4)
8 ; CHECK:Cluster ld/st SU(2) - SU(5)
9 ; CHECK:SU(4): STRXui %1:gpr64, %0:gpr64common, 1
10 ; CHECK:SU(3): STRXui %1:gpr64, %0:gpr64common, 2
11 ; CHECK:SU(2): STRXui %1:gpr64, %0:gpr64common, 3
12 ; CHECK:SU(5): STRXui %1:gpr64, %0:gpr64common, 4
28 ; CHECK:Cluster ld/st SU(3) - SU(4)
29 ; CHECK:Cluster ld/st SU(2) - SU(5)
30 ; CHECK:SU(4): STRWui %1:gpr32, %0:gpr64common, 1
31 ; CHECK:SU(3): STRWui %1:gpr32, %0:gpr64common, 2
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| D | misched-fusion-arith-logic.mir | 14 ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w1
16 ; CHECK: SU(2): Ord Latency=0 Cluster
17 ; CHECK: SU(1): %1:gpr32 = ADDWrr undef $w1, undef $w2
19 ; CHECK: SU(3): Ord Latency=0 Cluster
20 ; CHECK: SU(2): dead %2:gpr32 = SUBWrs %0:gpr32, undef $w2, 0
22 ; CHECK: SU(0): Ord Latency=0 Cluster
23 ; CHECK: SU(3): dead %3:gpr32 = ADDWrs %1:gpr32, undef $w3, 0
25 ; CHECK: SU(1): Ord Latency=0 Cluster
36 ; CHECK: SU(0): %0:gpr64 = ADDXrr undef $x0, undef $x1
38 ; CHECK: SU(2): Ord Latency=0 Cluster
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| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-stp-cluster.ll | 6 ; CHECK:Cluster ld/st SU(4) - SU(3)
7 ; CHECK:Cluster ld/st SU(2) - SU(5)
8 ; CHECK:SU(4): STRXui %vreg1, %vreg0, 1
9 ; CHECK:SU(3): STRXui %vreg1, %vreg0, 2
10 ; CHECK:SU(2): STRXui %vreg1, %vreg0, 3
11 ; CHECK:SU(5): STRXui %vreg1, %vreg0, 4
27 ; CHECK:Cluster ld/st SU(4) - SU(3)
28 ; CHECK:Cluster ld/st SU(2) - SU(5)
29 ; CHECK:SU(4): STRWui %vreg1, %vreg0, 1
30 ; CHECK:SU(3): STRWui %vreg1, %vreg0, 2
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| D | arm64-ldp-cluster.ll | 8 ; CHECK: Cluster ld/st SU(1) - SU(2)
9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
13 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
28 ; CHECK: Cluster ld/st SU(1) - SU(2)
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
33 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 46 getNumDecoderSlots(SUnit *SU) const { in getNumDecoderSlots()
47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const { in getCurrCycleIdx()
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) { in getCurrCycleIdx()
77 getHazardType(SUnit *SU, int Stalls) { in getHazardType() argument
78 return (fitsIntoCurrentGroup(SU) ? NoHazard : Hazard); in getHazardType()
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const { in fitsIntoCurrentGroup()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
111 assert ((getNumDecoderSlots(SU) <= 1) && (CurrGroupSize < 3) && in fitsIntoCurrentGroup()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 46 getNumDecoderSlots(SUnit *SU) const { in getNumDecoderSlots()
47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const { in getCurrCycleIdx()
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) { in getCurrCycleIdx()
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const { in fitsIntoCurrentGroup()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
111 assert ((getNumDecoderSlots(SU) <= 1) && (CurrGroupSize < 3) && in fitsIntoCurrentGroup()
167 void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const { in dumpSU() argument
168 OS << "SU(" << SU->NodeNum << "):"; in dumpSU()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 601 for (const SUnit *SU : Queue) in dump() local
602 dbgs() << SU->NodeNum << " "; in dump()
620 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
639 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
640 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
648 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
649 for (SDep &Succ : SU->Succs) in releaseSuccessors()
650 releaseSucc(SU, &Succ); in releaseSuccessors()
657 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
676 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
[all …]
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| D | ScheduleDAGInstrs.cpp | 229 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
246 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
247 if (UseSU == SU) in addPhysRegDataDeps()
256 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
260 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
261 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
272 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 233 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
242 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
248 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
249 if (UseSU == SU) in addPhysRegDataDeps()
258 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
262 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
263 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
272 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
274 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
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| D | MachineScheduler.cpp | 618 for (const SUnit *SU : Queue) in dump() local
619 dbgs() << SU->NodeNum << " "; in dump()
637 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
656 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
657 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
665 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
666 for (SDep &Succ : SU->Succs) in releaseSuccessors()
667 releaseSucc(SU, &Succ); in releaseSuccessors()
674 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
693 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
[all …]
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