1# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags | FileCheck %s 2# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -run-pass=machine-scheduler -misched-print-dags | FileCheck %s 3# REQUIRES: asserts 4 5--- 6name: arith 7body: | 8 bb.0.entry: 9 %0:gpr32 = SUBWrr undef $w0, undef $w1 10 %1:gpr32 = ADDWrr undef $w1, undef $w2 11 %2:gpr32 = SUBWrs %0, undef $w2, 0 12 %3:gpr32 = ADDWrs %1, undef $w3, 0 13 14 ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w1 15 ; CHECK: Successors: 16 ; CHECK: SU(2): Ord Latency=0 Cluster 17 ; CHECK: SU(1): %1:gpr32 = ADDWrr undef $w1, undef $w2 18 ; CHECK: Successors: 19 ; CHECK: SU(3): Ord Latency=0 Cluster 20 ; CHECK: SU(2): dead %2:gpr32 = SUBWrs %0:gpr32, undef $w2, 0 21 ; CHECK: Predecessors: 22 ; CHECK: SU(0): Ord Latency=0 Cluster 23 ; CHECK: SU(3): dead %3:gpr32 = ADDWrs %1:gpr32, undef $w3, 0 24 ; CHECK: Predecessors: 25 ; CHECK: SU(1): Ord Latency=0 Cluster 26... 27--- 28name: compare 29body: | 30 bb.0.entry: 31 %0:gpr64 = ADDXrr undef $x0, undef $x1 32 %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 33 %2:gpr64 = ADDSXrr %0, undef $x3, implicit-def $nzcv 34 %3:gpr64 = SUBSXrs %1, undef $x4, 0, implicit-def $nzcv 35 36 ; CHECK: SU(0): %0:gpr64 = ADDXrr undef $x0, undef $x1 37 ; CHECK: Successors: 38 ; CHECK: SU(2): Ord Latency=0 Cluster 39 ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 40 ; CHECK: Successors: 41 ; CHECK: SU(3): Ord Latency=0 Cluster 42 ; CHECK: SU(2): dead %2:gpr64 = ADDSXrr %0:gpr64, undef $x3, implicit-def $nzcv 43 ; CHECK: Predecessors: 44 ; CHECK: SU(0): Ord Latency=0 Cluster 45 ; CHECK: SU(3): dead %3:gpr64 = SUBSXrs %1:gpr64, undef $x4, 0, implicit-def $nzcv 46 ; CHECK: Predecessors: 47 ; CHECK: SU(1): Ord Latency=0 Cluster 48... 49--- 50name: logic 51body: | 52 bb.0.entry: 53 %0:gpr32 = ADDWrr undef $w0, undef $w1 54 %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 55 %3:gpr32 = ANDWrs %0, undef $w3, 0 56 %4:gpr64 = ORRXrr %1, undef $x4 57 58 ; CHECK: SU(0): %0:gpr32 = ADDWrr undef $w0, undef $w1 59 ; CHECK: Successors: 60 ; CHECK: SU(2): Ord Latency=0 Cluster 61 ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 62 ; CHECK: Successors: 63 ; CHECK: SU(3): Ord Latency=0 Cluster 64 ; CHECK: SU(2): dead %2:gpr32 = ANDWrs %0:gpr32, undef $w3, 0 65 ; CHECK: Predecessors: 66 ; CHECK: SU(0): Ord Latency=0 Cluster 67 ; CHECK: SU(3): dead %3:gpr64 = ORRXrr %1:gpr64, undef $x4 68 ; CHECK: Predecessors: 69 ; CHECK: SU(1): Ord Latency=0 Cluster 70... 71--- 72name: nope 73body: | 74 bb.0.entry: 75 ; Shifted register. 76 %0:gpr32 = SUBWrr undef $w0, undef $w1 77 %1:gpr32 = SUBWrs %0, undef $w2, 1 78 ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w1 79 ; CHECK: Successors: 80 ; CHECK-NOT: SU(1): Ord Latency=0 Cluster 81 ; CHECK: SU(1): dead %1:gpr32 = SUBWrs %0:gpr32, undef $w2, 1 82 83 ; Multiple successors. 84 %2:gpr64 = ADDXrr undef $x0, undef $x1 85 %3:gpr32 = EXTRACT_SUBREG %2, %subreg.sub_32 86 %4:gpr32 = ANDWrs %3, undef $w2, 0 87 %5:gpr64 = ADDSXrr %2, undef $x3, implicit-def $nzcv 88 ; CHECK: SU(2): %2:gpr64 = ADDXrr undef $x0, undef $x1 89 ; CHECK: Successors: 90 ; CHECK-NOT: SU(3): Ord Latency=0 Cluster 91 ; CHECK: SU(5): Ord Latency=0 Cluster 92 ; CHECK: SU(3): %3:gpr32 = EXTRACT_SUBREG %2:gpr64, %subreg.sub_32 93 ; CHECK: SU(5): dead %5:gpr64 = ADDSXrr %2:gpr64, undef $x3, implicit-def $nzcv 94 95 ; Different register sizes. 96 %6:gpr32 = SUBWrr undef $w0, undef $w1 97 %7:gpr64 = ADDXrr undef $x1, undef $x2 98 %8:gpr64 = SUBXrr %7, undef $x3 99 %9:gpr32 = ADDWrr %6, undef $w4 100 ; CHECK: SU(6): %6:gpr32 = SUBWrr undef $w0, undef $w1 101 ; CHECK: Successors: 102 ; CHECK-NOT: SU(8): Ord Latency=0 Cluster 103 ; CHECK: SU(7): %7:gpr64 = ADDXrr undef $x1, undef $x2 104 ; CHECK: Successors: 105 ; CHECK-NOT: SU(9): Ord Latency=0 Cluster 106 ; CHECK: SU(8): dead %8:gpr64 = SUBXrr %7:gpr64, undef $x3 107 ; CHECK: Predecessors: 108 ; CHECK: SU(7): Ord Latency=0 Cluster 109 ; CHECK: SU(9): dead %9:gpr32 = ADDWrr %6:gpr32, undef $w4 110 ; CHECK: Predecessors: 111 ; CHECK: SU(6): Ord Latency=0 Cluster 112... 113