| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | store_4_unaligned_r6.mir | 43 ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align1, align 1)
66 ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align8, align 8)
|
| D | store.mir | 53 ; MIPS32FP32: SWC1 [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
59 ; MIPS32FP64: SWC1 [[COPY]], [[COPY1]], 0 :: (store 4 into %ir.ptr)
|
| D | store_4_unaligned.mir | 69 ; MIPS32: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align4)
|
| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 238 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 230 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 238 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
205 Opc = Mips::SWC1; in storeRegToStack()
|
| D | MipsInstrFPU.td | 406 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
648 def : StoreRegImmPat<SWC1, f32>;
|
| D | MipsFastISel.cpp | 797 Opc = Mips::SWC1; in emitStore()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
267 Opc = Mips::SWC1; in storeRegToStack()
|
| D | MipsInstrFPU.td | 568 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
806 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
972 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1;
|
| D | MipsInstructionSelector.cpp | 222 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
|
| D | MipsScheduleP5600.td | 579 SWC1, SWXC1, SUXC1, SUXC164)>;
|
| D | MipsFastISel.cpp | 832 Opc = Mips::SWC1; in emitStore()
|
| D | MipsScheduleGeneric.td | 874 SUXC1, SUXC164, SWC1, SWXC1)>;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
267 Opc = Mips::SWC1; in storeRegToStack()
|
| D | MipsInstrFPU.td | 601 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
839 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
1005 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1;
|
| D | MipsInstructionSelector.cpp | 228 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
|
| D | MipsScheduleP5600.td | 580 SWC1, SWXC1, SUXC1, SUXC164)>;
|
| D | MipsFastISel.cpp | 831 Opc = Mips::SWC1; in emitStore()
|
| D | MipsScheduleGeneric.td | 877 SUXC1, SUXC164, SWC1, SWXC1)>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 509 ins = SWC1 | S(SLJIT_SP) | FT(float_arg_count) | IMM(offsets[arg_count]); in call_with_args()
|
| D | sljitNativeMIPS_common.c | 250 #define SWC1 (HI(57)) macro
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 326 # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
|
| /external/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 326 # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
|