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Searched refs:SetCC (Results 1 – 25 of 48) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/llvm/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
82 // SetCC instructions.
DX86ISelLowering.cpp15613 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
15617 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, in LowerSETCC()
15619 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
15621 return SetCC; in LowerSETCC()
15642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
15645 SetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, SetCC, in LowerSETCC()
15647 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
15649 return SetCC; in LowerSETCC()
15665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, in LowerSETCCE() local
15668 SetCC = DAG.getNode(ISD::AssertZext, DL, MVT::i8, SetCC, in LowerSETCCE()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
DX86ISelLowering.cpp22018 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); in LowerXALUO() local
22020 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
24006 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
24009 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
24011 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
24015 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
24017 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
24021 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
24024 SetCC = getSETCC(X86::COND_A, InvComi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
24028 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrPrefix.td2417 multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, ImmLeaf ZExtTy,
2420 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2422 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2424 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2426 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2428 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2431 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
2433 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
2435 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
2437 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
[all …]
DPPCInstrInfo.td3990 multiclass FSetCCPat<SDNode SetCC, ValueType Ty, PatLeaf FCmp> {
3991 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3993 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3995 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3997 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3999 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
4001 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
4003 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
4006 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
4008 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp681 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
683 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
684 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
708 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
711 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
712 SetCC.getOperand(1), in performSELECTCombine()
713 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
715 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
738 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
745 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
DMipsSEISelLowering.cpp985 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
991 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp582 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
584 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
585 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
609 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
612 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
613 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
615 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
638 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
645 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
646 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
DMipsSEISelLowering.cpp1027 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
1029 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
1033 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
1034 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.cpp682 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
684 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
685 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
709 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
712 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
713 SetCC.getOperand(1), in performSELECTCombine()
714 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
716 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
739 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
746 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
DMipsSEISelLowering.cpp985 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
991 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1261 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1264 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1267 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/external/llvm-project/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1368 SDNode *SetCC = nullptr; in LowerBRCOND() local
1372 SetCC = Intr; in LowerBRCOND()
1373 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
1386 assert(!SetCC || in LowerBRCOND()
1387 (SetCC->getConstantOperandVal(1) == 1 && in LowerBRCOND()
1388 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == in LowerBRCOND()
/external/llvm-project/llvm/test/CodeGen/X86/
Dopt-pipeline.ll112 ; CHECK-NEXT: X86 Fixup SetCC
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp2207 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
2208 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in foldAddSubBoolOfMaskedVal()
2209 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || in foldAddSubBoolOfMaskedVal()
2210 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2211 !isOneConstant(SetCC.getOperand(0).getOperand(1))) in foldAddSubBoolOfMaskedVal()
2220 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); in foldAddSubBoolOfMaskedVal()
7624 SDValue SetCC = in visitXOR() local
7627 CombineTo(N, SetCC); in visitXOR()
7628 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); in visitXOR()
10124 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
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