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Searched refs:SignBit (Results 1 – 25 of 35) sorted by relevance

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/external/llvm-project/llvm/include/llvm/DebugInfo/DWARF/
DDWARFExpression.h49 SignBit = 0x80, enumerator
50 SignedSize1 = SignBit | Size1,
51 SignedSize2 = SignBit | Size2,
52 SignedSize4 = SignBit | Size4,
53 SignedSize8 = SignBit | Size8,
54 SignedSizeLEB = SignBit | SizeLEB,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/DWARF/
DDWARFExpression.h45 SignBit = 0x80, enumerator
46 SignedSize1 = SignBit | Size1,
47 SignedSize2 = SignBit | Size2,
48 SignedSize4 = SignBit | Size4,
49 SignedSize8 = SignBit | Size8,
50 SignedSizeLEB = SignBit | SizeLEB,
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp321 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
325 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
330 SignBit = in SoftenFloatRes_FCOPYSIGN()
331 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
333 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
335 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
337 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
338 SignBit = in SoftenFloatRes_FCOPYSIGN()
339 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
341 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
[all …]
DLegalizeDAG.cpp71 uint8_t SignBit; member
1484 State.SignBit = NumBits - 1; in getSignAsIntValue()
1520 State.SignBit = 7; in getSignAsIntValue()
1549 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1558 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1572 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1574 if (SignBit.getScalarValueSizeInBits() < in ExpandFCOPYSIGN()
1576 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1581 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1584 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
[all …]
/external/llvm-project/flang/lib/Decimal/
Dbig-radix-floating-point.h343 constexpr Raw SignBit() const { return Raw{isNegative_} << (Real::bits - 1); } in RemoveLeastOrderZeroDigits() function
345 return (Raw{Real::maxExponent} << Real::significandBits) | SignBit(); in RemoveLeastOrderZeroDigits()
Ddecimal-to-binary.cpp311 return {Real{SignBit()}}; in ConvertToBinary()
320 return {Real{SignBit()}, Inexact}; in ConvertToBinary()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp135 unsigned Signed = Size & Operation::SignBit; in extract()
140 switch (Size & ~Operation::SignBit) { in extract()
259 unsigned Signed = Size & Operation::SignBit; in print()
/external/llvm-project/clang/lib/AST/Interp/
DIntegral.h144 const T SignBit = T(1) << (TruncBits - 1);
146 return Integral((V & BitMask) | (Signed && (V & SignBit) ? ExtMask : 0));
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp262 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
266 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
271 SignBit = in SoftenFloatRes_FCOPYSIGN()
272 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
274 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
276 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
278 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
279 SignBit = in SoftenFloatRes_FCOPYSIGN()
280 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
282 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
[all …]
DLegalizeDAG.cpp1359 uint8_t SignBit; member
1377 State.SignBit = NumBits - 1; in getSignAsIntValue()
1414 State.SignBit = 7; in getSignAsIntValue()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1467 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1468 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1476 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
[all …]
DTargetLowering.cpp836 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); in SimplifyDemandedBits() local
840 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { in SimplifyDemandedBits()
858 if (KnownOne.intersects(SignBit)) in SimplifyDemandedBits()
DDAGCombiner.cpp7476 SDValue SignBit = DAG.getConstant( in visitBITCAST() local
7480 FlipBit = SignBit; in visitBITCAST()
7489 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); in visitBITCAST()
7497 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
7500 NewConv, DAG.getConstant(SignBit, DL, VT)); in visitBITCAST()
7503 NewConv, DAG.getConstant(~SignBit, DL, VT)); in visitBITCAST()
7545 APInt SignBit = APInt::getSignBit(VT.getSizeInBits() / 2); in visitBITCAST() local
7559 DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); in visitBITCAST()
7566 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
7568 X, DAG.getConstant(SignBit, SDLoc(X), VT)); in visitBITCAST()
[all …]
DSelectionDAG.cpp2198 APInt SignBit = APInt::getSignBit(BitWidth); in computeKnownBits() local
2199 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. in computeKnownBits()
2201 if (KnownZero.intersects(SignBit)) { in computeKnownBits()
2203 } else if (KnownOne.intersects(SignBit)) { in computeKnownBits()
/external/llvm-project/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp132 unsigned Signed = Size & Operation::SignBit; in extract()
137 switch (Size & ~Operation::SignBit) { in extract()
281 unsigned Signed = Size & Operation::SignBit; in print()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp302 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
306 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
311 SignBit = in SoftenFloatRes_FCOPYSIGN()
312 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
314 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
316 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
318 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
319 SignBit = in SoftenFloatRes_FCOPYSIGN()
320 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
322 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
[all …]
DLegalizeDAG.cpp71 uint8_t SignBit; member
1454 State.SignBit = NumBits - 1; in getSignAsIntValue()
1489 State.SignBit = 7; in getSignAsIntValue()
1518 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1527 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1541 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1543 if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1544 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1549 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1552 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
[all …]
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp655 APInt SignBit(APInt::getSignBit(BitWidth)); in SimplifyDemandedUseBits() local
657 SignBit = APIntOps::lshr(SignBit, ShiftAmt); in SimplifyDemandedUseBits()
668 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. in SimplifyDemandedUseBits()
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DKnownBitsTest.cpp315 auto SignBit = B.buildConstant(S32, 0x80000000); in TEST_F() local
321 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0))); in TEST_F()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp973 APInt SignBit = APInt::getSignMask(32); in PerformDAGCombine() local
976 DAG.getConstant(SignBit, DL, MVT::i32)); in PerformDAGCombine()
981 DAG.getConstant(~SignBit, DL, MVT::i32)); in PerformDAGCombine()
1018 APInt SignBit = APInt::getSignMask(32).sext(64); in PerformDAGCombine() local
1022 DAG.getConstant(SignBit, DL, MVT::i64))); in PerformDAGCombine()
1027 DAG.getConstant(~SignBit, DL, MVT::i64))); in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp1482 APInt SignBit = APInt::getSignMask(32); in PerformDAGCombine() local
1485 DAG.getConstant(SignBit, DL, MVT::i32)); in PerformDAGCombine()
1490 DAG.getConstant(~SignBit, DL, MVT::i32)); in PerformDAGCombine()
1563 APInt SignBit = APInt::getSignMask(32).sext(64); in PerformDAGCombine() local
1566 DAG.getConstant(SignBit, DL, MVT::i64)); in PerformDAGCombine()
1570 DAG.getConstant(~SignBit, DL, MVT::i64)); in PerformDAGCombine()
/external/tensorflow/tensorflow/python/lib/core/
Dbfloat16.cc1088 struct SignBit { struct
1587 RegisterUFunc<UnaryUFunc<bfloat16, bool, ufuncs::SignBit>>(numpy.get(), in Initialize()
/external/llvm/lib/Support/
DAPInt.cpp1068 unsigned SignBit = APINT_BITS_PER_WORD - BitWidth; in ashr() local
1070 (((int64_t(VAL) << SignBit) >> SignBit) >> shiftAmt)); in ashr()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1664 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC() local
1667 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
1930 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32() local
1931 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp1452 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc() local
1459 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)}); in legalizeIntrinsicTrunc()
DAMDGPUISelLowering.cpp2100 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC() local
2103 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2423 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32() local
2424 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()

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