| /external/llvm-project/llvm/utils/TableGen/ |
| D | InfoByHwMode.cpp | 124 SpillSize = R->getValueAsInt("SpillSize"); in RegSizeInfo()
129 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
130 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
136 SpillSize <= I.SpillSize; in isSubClassOf()
140 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
174 return std::tie(A0.SpillSize, A0.SpillAlignment) > in hasStricterSpillThan()
175 std::tie(B0.SpillSize, B0.SpillAlignment); in hasStricterSpillThan()
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| D | InfoByHwMode.h | 150 unsigned SpillSize; member
157 return std::tie(RegSize, SpillSize, SpillAlignment) ==
158 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| D | RegisterBankEmitter.cpp | 88 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
89 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
250 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
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| D | RegisterInfoEmitter.cpp | 1295 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1649 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
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| D | CodeGenRegisters.cpp | 798 RI.RegSize = RI.SpillSize = Size ? Size in CodeGenRegisterClass()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 303 unsigned SpillSize; variable
407 unsigned SpillSize; member
411 : Members(M), SpillSize(S), SpillAlignment(A) {} in Members()
415 SpillSize(RC.SpillSize), in Key()
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| D | CodeGenRegisters.cpp | 708 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits(); in CodeGenRegisterClass()
729 SpillSize(Props.SpillSize), in CodeGenRegisterClass()
771 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment; in operator <<()
783 return std::tie(*Members, SpillSize, SpillAlignment) < in operator <()
784 std::tie(*B.Members, B.SpillSize, B.SpillAlignment); in operator <()
799 A->SpillSize <= B->SpillSize && in testSubClass()
819 if (A->SpillSize < B->SpillSize) in TopoOrderRC()
821 if (A->SpillSize > B->SpillSize) in TopoOrderRC()
1052 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment); in getOrCreateSubClass()
1892 if (RC2->SpillSize > RC1->SpillSize || in inferCommonSubClass()
[all …]
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| D | RegisterInfoEmitter.cpp | 1032 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); in runMCDesc()
1040 << RC.SpillSize/8 << ", " in runMCDesc()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | StatepointLowering.cpp | 75 unsigned SpillSize = ValueType.getSizeInBits() / 8; in allocateStackSlot() local
76 assert((SpillSize * 8) == ValueType.getSizeInBits() && "Size not in bytes?"); in allocateStackSlot()
93 if (MFI->getObjectSize(FI) == SpillSize) { in allocateStackSlot()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
278 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
278 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | StatepointLowering.cpp | 98 unsigned SpillSize = ValueType.getStoreSize(); in allocateStackSlot() local
99 assert((SpillSize * 8) == ValueType.getSizeInBits() && "Size not in bytes?"); in allocateStackSlot()
115 if (MFI.getObjectSize(FI) == SpillSize) { in allocateStackSlot()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | StatepointLowering.cpp | 111 unsigned SpillSize = ValueType.getStoreSize(); in allocateStackSlot() local
112 assert((SpillSize * 8) == ValueType.getSizeInBits() && "Size not in bytes?"); in allocateStackSlot()
128 if (MFI.getObjectSize(FI) == SpillSize) { in allocateStackSlot()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 471 unsigned SpillSize; in foldPatchpoint() local
477 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
481 MIB.addImm(SpillSize); in foldPatchpoint()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 512 unsigned SpillSize; in foldPatchpoint() local
518 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
522 MIB.addImm(SpillSize); in foldPatchpoint()
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| D | LiveDebugVariables.cpp | 1202 unsigned SpillSize; in rewriteLocations() local
1205 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 537 unsigned SpillSize; in foldPatchpoint() local
543 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
547 MIB.addImm(SpillSize); in foldPatchpoint()
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| D | LiveDebugVariables.cpp | 1229 unsigned SpillSize; in rewriteLocations() local
1232 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1068 unsigned SpillSize = TRI->getSpillSize(*RC); in storeRegToStackSlot() local
1076 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot()
1080 if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) { in storeRegToStackSlot()
1099 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1100 : getVGPRSpillSaveOpcode(SpillSize); in storeRegToStackSlot()
1191 unsigned SpillSize = TRI->getSpillSize(*RC); in loadRegFromStackSlot() local
1205 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot()
1206 if (Register::isVirtualRegister(DestReg) && SpillSize == 4) { in loadRegFromStackSlot()
1221 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
1222 : getVGPRSpillRestoreOpcode(SpillSize); in loadRegFromStackSlot()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1408 unsigned SpillSize = TRI->getSpillSize(*RC); in storeRegToStackSlot() local
1418 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot()
1422 if (SrcReg.isVirtual() && SpillSize == 4) { in storeRegToStackSlot()
1438 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1439 : getVGPRSpillSaveOpcode(SpillSize); in storeRegToStackSlot()
1534 unsigned SpillSize = TRI->getSpillSize(*RC); in loadRegFromStackSlot() local
1551 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot()
1552 if (DestReg.isVirtual() && SpillSize == 4) { in loadRegFromStackSlot()
1567 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
1568 : getVGPRSpillRestoreOpcode(SpillSize); in loadRegFromStackSlot()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1954 const uint64_t SpillSize = 4; // Condition register is always 4 bytes. in determineCalleeSaves() local
1958 MFI.CreateFixedObject(SpillSize, SpillOffset, in determineCalleeSaves()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 5410 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode() local
5411 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
5417 switch (SpillSize) { in getBroadcastOpcode()
5425 switch (SpillSize) { in getBroadcastOpcode()
5433 switch (SpillSize) { in getBroadcastOpcode()
5441 switch (SpillSize) { in getBroadcastOpcode()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 6166 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode() local
6167 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
6173 switch (SpillSize) { in getBroadcastOpcode()
6181 switch (SpillSize) { in getBroadcastOpcode()
6189 switch (SpillSize) { in getBroadcastOpcode()
6197 switch (SpillSize) { in getBroadcastOpcode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 62 int SpillSize = SS; // Spill slot size in bits.
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | Target.td | 62 int SpillSize = SS; // Spill slot size in bits.
|