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Searched refs:SrcRC (Results 1 – 25 of 114) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp135 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
148 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
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DSILowerI1Copies.cpp103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
106 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
133 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr in copyPhysReg()
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr in copyPhysReg()
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp174 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg) in getCopyRegClasses() local
185 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
188 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
192 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
195 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
198 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
261 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
262 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
264 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
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DAMDGPUInstructionSelector.cpp115 const TargetRegisterClass *SrcRC in selectCOPY() local
118 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
124 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY()
134 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
151 const TargetRegisterClass *SrcRC = in selectCOPY() local
153 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectCOPY()
463 const TargetRegisterClass *SrcRC = in selectG_EXTRACT() local
465 if (!SrcRC) in selectG_EXTRACT()
468 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_EXTRACT()
511 const TargetRegisterClass *SrcRC in selectG_MERGE_VALUES() local
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp173 const TargetRegisterClass *SrcRC = SrcReg.isVirtual() in getCopyRegClasses() local
184 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
187 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
190 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
191 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
194 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
197 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
259 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
260 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
262 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
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DAMDGPUInstructionSelector.cpp114 const TargetRegisterClass *SrcRC in constrainCopyLikeIntrin() local
116 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
147 const TargetRegisterClass *SrcRC in selectCOPY() local
150 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
156 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY()
166 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
482 const TargetRegisterClass *SrcRC = in selectG_EXTRACT() local
484 if (!SrcRC) in selectG_EXTRACT()
488 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg); in selectG_EXTRACT()
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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
41 if (DestRC->getSize() != SrcRC->getSize()) in copyPhysReg()
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp292 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
295 if (DefRC == SrcRC) in shareSameRegisterFile()
301 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
309 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
314 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
317 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
322 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
325 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
162 if (DstRC == SrcRC) in isCrossCopy()
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
193 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp112 const TargetRegisterClass *SrcRC) const;
248 const TargetRegisterClass *SrcRC = in selectCopy() local
252 if (SrcRC != DstRC) { in selectCopy()
260 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
286 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
288 if (DstRC != SrcRC) { in selectCopy()
685 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY() argument
688 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
694 const TargetRegisterClass *SrcRC) const { in selectTurnIntoCOPY()
696 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp111 const TargetRegisterClass *SrcRC) const;
247 const TargetRegisterClass *SrcRC = in selectCopy() local
251 if (SrcRC != DstRC) { in selectCopy()
259 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
285 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
287 if (DstRC != SrcRC) { in selectCopy()
684 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY() argument
687 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
693 const TargetRegisterClass *SrcRC) const { in selectTurnIntoCOPY()
695 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp345 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
348 if (DefRC == SrcRC) in shareSameRegisterFile()
354 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
362 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
367 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
370 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
375 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
378 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
159 if (DstRC == SrcRC) in isCrossCopy()
184 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
187 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
189 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
190 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
/external/llvm-project/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp365 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
368 if (DefRC == SrcRC) in shareSameRegisterFile()
374 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
382 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
387 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
390 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
395 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
398 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp155 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
156 if (DstRC == SrcRC) in isCrossCopy()
181 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
184 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
186 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
187 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp106 const TargetRegisterClass *SrcRC = in processBlock() local
115 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrFPU.td125 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
127 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
132 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
135 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
159 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
161 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
162 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
166 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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DMicroMips32r6InstrInfo.td658 RegisterOperand SrcRC, InstrItinClass Itin> {
659 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
668 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
671 dag InOperandList = (ins SrcRC:$rt);
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
680 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
694 RegisterOperand SrcRC, InstrItinClass Itin> {
695 dag InOperandList = (ins SrcRC:$rt);
716 RegisterOperand SrcRC, InstrItinClass Itin> {
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/external/llvm-project/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td658 RegisterOperand SrcRC, InstrItinClass Itin> {
659 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
668 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
671 dag InOperandList = (ins SrcRC:$rt);
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
680 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
694 RegisterOperand SrcRC, InstrItinClass Itin> {
695 dag InOperandList = (ins SrcRC:$rt);
716 RegisterOperand SrcRC, InstrItinClass Itin> {
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DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td669 RegisterOperand SrcRC> {
670 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
678 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
681 dag InOperandList = (ins SrcRC:$rt);
684 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
690 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
692 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
704 RegisterOperand SrcRC> {
705 dag InOperandList = (ins SrcRC:$rt);
725 RegisterOperand SrcRC> {
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