| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 168 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, in packRegs() argument
170 assert(SrcRegs.size() > 1 && "Nothing to pack"); in packRegs()
180 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); in packRegs()
184 for (unsigned i = 0; i < SrcRegs.size(); ++i) { in packRegs()
186 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); in packRegs()
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| D | InlineAsmLowering.cpp | 458 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
459 assert(SrcRegs.size() == 1 && "Single register is expected here"); in lowerInlineAsm()
462 Register In = SrcRegs[0]; in lowerInlineAsm()
466 if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) in lowerInlineAsm()
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| D | LegalizerHelper.cpp | 1066 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); in narrowScalar() local
1072 SrcRegs[i / 2]); in narrowScalar()
1081 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1172 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1178 SrcRegs.push_back(SrcReg); in narrowScalar()
1182 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); in narrowScalar()
1193 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
1210 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) in narrowScalar()
1228 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
1230 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); in narrowScalar()
[all …]
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| D | IRTranslator.cpp | 1376 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
1382 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
1393 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1401 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
1555 SmallVector<Register, 3> SrcRegs; in translateMemFunc() local
1563 SrcRegs.push_back(SrcReg); in translateMemFunc()
1569 Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1]; in translateMemFunc()
1574 for (Register SrcReg : SrcRegs) in translateMemFunc()
2717 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); in translateFreeze() local
2719 assert(DstRegs.size() == SrcRegs.size() && in translateFreeze()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 130 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, in packRegs() argument
132 assert(SrcRegs.size() > 1 && "Nothing to pack"); in packRegs()
142 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); in packRegs()
146 for (unsigned i = 0; i < SrcRegs.size(); ++i) { in packRegs()
148 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); in packRegs()
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| D | LegalizerHelper.cpp | 914 SmallVector<SmallVector<Register, 2>, 2> SrcRegs; in narrowScalar() local
916 SrcRegs.resize(MI.getNumOperands() / 2); in narrowScalar()
922 SrcRegs[i / 2]); in narrowScalar()
931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1024 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1030 SrcRegs.push_back(SrcReg); in narrowScalar()
1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg()); in narrowScalar()
1046 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
1065 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) in narrowScalar()
1084 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
[all …]
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| D | IRTranslator.cpp | 975 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
981 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
992 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1000 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 757 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
759 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
771 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 762 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
764 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
766 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
769 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
776 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1458 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1468 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1469 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1483 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1485 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1556 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1566 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1567 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
1588 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1491 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1501 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1502 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1516 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1518 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1589 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1599 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1600 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
1621 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 668 MachineIRBuilder &B, ArrayRef<Register> DstRegs, ArrayRef<Register> SrcRegs) { in mergeVectorRegsToResultRegs() argument
671 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
678 return B.buildConcatVectors(DstRegs[0], SrcRegs); in mergeVectorRegsToResultRegs()
688 std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin()); in mergeVectorRegsToResultRegs()
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| D | AMDGPURegisterBankInfo.cpp | 1203 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingLoad() local
1205 if (SrcRegs.empty()) in applyMappingLoad()
1206 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingLoad()
1212 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad()
2476 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
2477 if (SrcRegs.empty()) in applyMappingImpl()
2495 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2498 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt); in applyMappingImpl()
2504 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 233 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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| D | LegalizationArtifactCombiner.h | 270 SmallVector<Register, 8> SrcRegs(NumSrcs); in tryCombineTrunc()
272 SrcRegs[i] = SrcMI->getOperand(i + 1).getReg(); in tryCombineTrunc()
274 Builder.buildMerge(DstReg, SrcRegs); in tryCombineTrunc()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 715 const SmallVectorImpl<TargetInstrInfo::RegSubRegPair> &SrcRegs, in insertPHI() argument
717 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
719 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg); in insertPHI()
726 for (auto RegPair : SrcRegs) { in insertPHI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1125 SmallVector<unsigned, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingWideLoad() local
1128 if (SrcRegs.empty()) { in applyMappingWideLoad()
1133 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingWideLoad()
1145 Register BasePtrReg = SrcRegs[0]; in applyMappingWideLoad()
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