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Searched refs:StartReg (Results 1 – 4 of 4) sorted by relevance

/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNNSAReassign.cpp89 unsigned StartReg) const;
91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
113 unsigned StartReg) const { in tryAssignRegisters()
121 if (LRM->checkInterference(*Intervals[N], MCRegister::from(StartReg + N))) in tryAssignRegisters()
125 LRM->assign(*Intervals[N], MCRegister::from(StartReg + N)); in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign() argument
132 unsigned Reg = StartReg + N; in canAssign()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNNSAReassign.cpp89 unsigned StartReg) const;
91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
113 unsigned StartReg) const { in tryAssignRegisters()
121 if (LRM->checkInterference(*Intervals[N], StartReg + N)) in tryAssignRegisters()
125 LRM->assign(*Intervals[N], StartReg + N); in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign() argument
132 unsigned Reg = StartReg + N; in canAssign()
/external/llvm-project/llvm/lib/Target/ARM/
DMVEVPTOptimisationsPass.cpp149 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch in findLoopComponents() local
152 LoopStart = LookThroughCOPY(MRI->getVRegDef(StartReg), MRI); in findLoopComponents()
DARMLowOverheadLoops.cpp628 Register StartReg = isDo(Start) ? Start->getOperand(1).getReg() in ValidateTailPredicate() local
630 if (StartInsertPt == Start && StartReg == ARM::LR) { in ValidateTailPredicate()