| /external/llvm-project/llvm/test/TableGen/ |
| D | ConcatenatedSubregs.td | 103 // CHECK-NEXT: SubReg ssub0 = S0
104 // CHECK-NEXT: SubReg ssub1 = S1
108 // CHECK-NEXT: SubReg ssub0 = S9
109 // CHECK-NEXT: SubReg ssub1 = S10
110 // CHECK-NEXT: SubReg ssub2 = S11
111 // CHECK-NEXT: SubReg ssub3 = S12
112 // CHECK-NEXT: SubReg ssub4 = S13
113 // CHECK-NEXT: SubReg sub0 = S9_S10
114 // CHECK-NEXT: SubReg sub1 = S11_S12
115 // CHECK-NEXT: SubReg ssub1_ssub2 = D5
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
|
| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsOptionRecord.cpp | 77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
|
| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
[all …]
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| D | PeepholeOptimizer.cpp | 160 bool findNextSource(unsigned Reg, unsigned SubReg,
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { in ValueTrackerResult() argument
226 addSource(Reg, SubReg); in ValueTrackerResult()
257 return RegSrcs[Idx].SubReg; in getSrcSubReg()
616 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, in findNextSource() argument
627 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg); in findNextSource()
638 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, in findNextSource()
676 CurSrcPair.SubReg = Res.getSrcSubReg(0); in findNextSource()
685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, in findNextSource()
686 CurSrcPair.SubReg); in findNextSource()
[all …]
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
175 unsigned SubReg = MO.getSubReg(); in extendToUses() local
176 if (SubReg != 0) { in extendToUses()
177 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| D | DetectDeadLanes.cpp | 180 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
181 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
453 if (SubReg == 0) in determineInitialUsedLanes()
456 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
464 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
[all …]
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| D | LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg(); in calculate() local
69 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
70 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
168 unsigned SubReg = MO.getSubReg(); in extendToUses() local
169 if (SubReg != 0) { in extendToUses()
170 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| D | PeepholeOptimizer.cpp | 297 ValueTrackerResult(Register Reg, unsigned SubReg) { in ValueTrackerResult() argument
298 addSource(Reg, SubReg); in ValueTrackerResult()
333 return RegSrcs[Idx].SubReg; in getSrcSubReg()
687 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
737 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
738 CurSrcPair.SubReg)) in findNextSource()
743 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
769 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
777 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1059 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
[all …]
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| D | PeepholeOptimizer.cpp | 294 ValueTrackerResult(unsigned Reg, unsigned SubReg) { in ValueTrackerResult() argument
295 addSource(Reg, SubReg); in ValueTrackerResult()
330 return RegSrcs[Idx].SubReg; in getSrcSubReg()
682 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
733 CurSrcPair.SubReg)) in findNextSource()
738 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
772 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 79 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
81 unsigned SubReg; member in __anondebd7f180111::GCNRegBankReassign::OperandMask
89 : MI(mi), Reg(reg), SubReg(subreg), FreeBanks(freebanks) {} in Candidate()
102 unsigned SubReg; member in __anondebd7f180111::GCNRegBankReassign::Candidate
184 unsigned getPhysRegBank(Register Reg, unsigned SubReg) const;
190 uint32_t getRegBankMask(Register Reg, unsigned SubReg, int Bank);
198 unsigned SubReg = 0, int Bank = -1);
219 unsigned getFreeBanks(Register Reg, unsigned SubReg, unsigned Mask,
238 unsigned SubReg = 0, int Bank = -1,
244 unsigned SubReg) const;
[all …]
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| D | SIRegisterInfo.h | 243 unsigned SubReg,
290 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
310 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
311 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
315 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
316 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
114 if (SubReg) in isGPR64()
121 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
125 SubReg == 0) || in isFPR64()
127 SubReg == AArch64::dsub); in isFPR64()
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
137 unsigned &SubReg) { in getSrcFromCopy() argument
138 SubReg = 0; in getSrcFromCopy()
146 SubReg = AArch64::dsub; in getSrcFromCopy()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 78 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
80 unsigned SubReg; member in __anon8074828c0111::GCNRegBankReassign::OperandMask
171 unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank);
198 unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask,
232 Printable printReg(unsigned Reg, unsigned SubReg = 0) const { in printReg() argument
233 return Printable([Reg, SubReg, this](raw_ostream &OS) { in printReg()
243 if (SubReg) in printReg()
244 OS << ':' << TRI->getSubRegIndexName(SubReg); in printReg()
295 unsigned GCNRegBankReassign::getRegBankMask(unsigned Reg, unsigned SubReg, in getRegBankMask() argument
304 if (SubReg) in getRegBankMask()
[all …]
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
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| /external/llvm-project/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 34 class GP8<GPR SubReg, string n> : PPCReg<n> {
35 let HWEncoding = SubReg.HWEncoding;
36 let SubRegs = [SubReg];
41 class SPE<GPR SubReg, string n> : PPCReg<n> {
42 let HWEncoding = SubReg.HWEncoding;
43 let SubRegs = [SubReg];
58 class QFPR<FPR SubReg, string n> : PPCReg<n> {
59 let HWEncoding = SubReg.HWEncoding;
60 let SubRegs = [SubReg];
72 class VR<VF SubReg, string n> : PPCReg<n> {
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 359 unsigned SubReg; member
360 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
361 : Reg(Reg), SubReg(SubReg) {} in Reg()
368 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1504 std::make_pair(Val.Reg, Val.SubReg);
1510 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 452 unsigned SubReg; member
454 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
455 : Reg(Reg), SubReg(SubReg) {} in Reg()
458 return Reg == P.Reg && SubReg == P.SubReg;
471 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
473 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1843 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1850 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
|