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Searched refs:TestReg (Results 1 – 9 of 9) sorted by relevance

/external/llvm-project/llvm/test/TableGen/
Dambiguous-composition.td24 class TestReg<string n, list<Register> s> : RegisterWithSubRegs<n, s> {
43 class FPR32<string n> : TestReg<n, []> {
46 class FPR64<string n, FPR32 high> : TestReg<n, [high]> {
50 class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {
54 class VPR128<string n, FPR64 high> : TestReg<n, [high]> {
75 class GPR32<string n> : TestReg<n, []> {
78 class GPR64<string n, GPR32 low> : TestReg<n, [low]> {
82 class GPR128<string n, GPR64 low> : TestReg<n, [low]> {
DConstraintChecking.inc9 class TestReg<string name, bits<1> enc> : Register<name, []> {
14 def R0 : TestReg<"R0", 0>;
15 def R1 : TestReg<"R1", 1>;
DHwModeSelect.td18 def TestReg : Register<"testreg">;
19 def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>;
DDAGDefaultOps.td18 class TestReg<int index> : Register<"R"#index, []> {
23 def "R"#i : TestReg<i>;
/external/python/cpython3/Modules/_ctypes/
D_ctypes_test.c59 } TestReg; typedef
62 EXPORT(TestReg) last_tfrsuv_arg = {0};
66 _testfunc_reg_struct_update_value(TestReg in) in _testfunc_reg_struct_update_value()
69 ((volatile TestReg *)&in)->first = 0x0badf00d; in _testfunc_reg_struct_update_value()
70 ((volatile TestReg *)&in)->second = 0x0badf00d; in _testfunc_reg_struct_update_value()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp272 MachineInstr *emitTestBit(Register TestReg, uint64_t Bit, bool IsNegative,
1290 Register TestReg; in getTestBitReg() local
1296 TestReg = MI->getOperand(1).getReg(); in getTestBitReg()
1303 std::swap(ConstantReg, TestReg); in getTestBitReg()
1313 TestReg = MI->getOperand(1).getReg(); in getTestBitReg()
1323 if (!C || !TestReg.isValid()) in getTestBitReg()
1329 unsigned TestRegSize = MRI.getType(TestReg).getSizeInBits(); in getTestBitReg()
1336 NextReg = TestReg; in getTestBitReg()
1342 NextReg = TestReg; in getTestBitReg()
1349 NextReg = TestReg; in getTestBitReg()
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/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp556 TestReg = InProlog ? (unsigned)X86::RDX in emitStackProbeInline() local
602 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg) in emitStackProbeInline()
606 .addReg(TestReg) in emitStackProbeInline()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FrameLowering.cpp593 TestReg = InProlog ? X86::RDX in emitStackProbeInline() local
653 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg) in emitStackProbeInline()
657 .addReg(TestReg) in emitStackProbeInline()
/external/llvm-project/llvm/lib/Target/X86/
DX86FrameLowering.cpp785 TestReg = InProlog ? X86::RDX in emitStackProbeInlineWindowsCoreCLR64() local
845 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg) in emitStackProbeInlineWindowsCoreCLR64()
849 .addReg(TestReg) in emitStackProbeInlineWindowsCoreCLR64()