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Searched refs:UREM (Results 1 – 25 of 133) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/InstCombine/
Dudivrem-change-width.ll110 ; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32
111 ; CHECK-NEXT: ret i32 [[UREM]]
122 ; CHECK-NEXT: [[UREM:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
123 ; CHECK-NEXT: ret <2 x i32> [[UREM]]
135 ; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], [[ZB]]
137 ; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[UREM]], [[EXTRA_USES]]
151 ; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32
152 ; CHECK-NEXT: ret i32 [[UREM]]
209 ; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32
210 ; CHECK-NEXT: ret i32 [[UREM]]
[all …]
Dadd4.ll6 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
7 ; CHECK-NEXT: ret i64 [[UREM]]
20 ; CHECK-NEXT: [[UREM:%.*]] = urem <2 x i64> [[X:%.*]], <i64 19136, i64 19136>
21 ; CHECK-NEXT: ret <2 x i64> [[UREM]]
33 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
34 ; CHECK-NEXT: ret i64 [[UREM]]
Drem.ll327 ; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], [[X:%.*]]
328 ; CHECK-NEXT: ret i64 [[UREM]]
341 ; CHECK-NEXT: [[UREM:%.*]] = zext i32 [[TMP2]] to i64
342 ; CHECK-NEXT: ret i64 [[UREM]]
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-legalize-urem.mir77 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $al = COPY [[UREM]](s8)
136 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
137 ; CHECK: $ax = COPY [[UREM]](s16)
191 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
192 ; CHECK: $eax = COPY [[UREM]](s32)
244 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
245 ; CHECK: $rax = COPY [[UREM]](s64)
Dx86-legalize-urem.mir76 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[LOAD]], [[LOAD1]]
77 ; CHECK: $al = COPY [[UREM]](s8)
138 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[LOAD]], [[LOAD1]]
139 ; CHECK: $ax = COPY [[UREM]](s16)
200 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[LOAD]], [[LOAD1]]
201 ; CHECK: $eax = COPY [[UREM]](s32)
Dx86_64-irtranslator.ll322 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
323 ; CHECK: $al = COPY [[UREM]](s8)
337 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
338 ; CHECK: $ax = COPY [[UREM]](s16)
350 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
351 ; CHECK: $eax = COPY [[UREM]](s32)
363 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
364 ; CHECK: $rax = COPY [[UREM]](s64)
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp429 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
433 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
437 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
441 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
446 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
450 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
454 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
458 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Drem_and_div.mir93 ; MIPS32: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY1]], [[COPY]]
94 ; MIPS32: $v0 = COPY [[UREM]](s32)
Drem_and_div_vec.mir390 ; P5600: [[UREM:%[0-9]+]]:fprb(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
391 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
419 ; P5600: [[UREM:%[0-9]+]]:fprb(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
420 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
448 ; P5600: [[UREM:%[0-9]+]]:fprb(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
449 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
477 ; P5600: [[UREM:%[0-9]+]]:fprb(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
478 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Drem_and_div_vec.mir377 ; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
378 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
405 ; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
406 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
433 ; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
434 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
461 ; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
462 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
Drem_and_div_vec_builtin.mir405 ; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
406 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
433 ; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
434 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
461 ; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
462 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
489 ; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
490 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
Drem_and_div.mir431 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
432 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
465 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
466 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
494 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
495 ; MIPS32: $v0 = COPY [[UREM]](s32)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp690 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
694 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
698 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
702 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
707 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
711 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
715 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
719 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
980 case ISD::UREM: in isHardwareLoopProfitable()
/external/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h73 case ISD::UREM:
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h95 case ISD::UREM:
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiTargetTransformInfo.h99 case ISD::UREM:
/external/llvm-project/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp1168 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1172 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1176 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1180 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1185 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1189 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1193 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1197 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1609 case ISD::UREM: in maybeLoweredToCall()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp255 ISD == ISD::UREM) && in getArithmeticInstrCost()
328 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
348 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
374 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
389 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
393 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
408 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
412 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
416 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h238 UREM, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp249 ISD == ISD::UREM) && in getArithmeticInstrCost()
353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Durem-opt-size.ll6 ; When the processor features hardware division, UDIV + UREM can be turned
/external/llvm/test/CodeGen/ARM/
Ddivmod-eabi.ll3 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1679 case ISD::UREM: in selectDivRem()
1696 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1803 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
1804 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()

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