1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s 3 4define i8 @zext_i1_to_i8(i1 %val) { 5 ; CHECK-LABEL: name: zext_i1_to_i8 6 ; CHECK: bb.1 (%ir-block.0): 7 ; CHECK: liveins: $edi 8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 9 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 10 ; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1) 11 ; CHECK: $al = COPY [[ZEXT]](s8) 12 ; CHECK: RET 0, implicit $al 13 %res = zext i1 %val to i8 14 ret i8 %res 15} 16 17define i16 @zext_i1_to_i16(i1 %val) { 18 ; CHECK-LABEL: name: zext_i1_to_i16 19 ; CHECK: bb.1 (%ir-block.0): 20 ; CHECK: liveins: $edi 21 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 22 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 23 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s1) 24 ; CHECK: $ax = COPY [[ZEXT]](s16) 25 ; CHECK: RET 0, implicit $ax 26 %res = zext i1 %val to i16 27 ret i16 %res 28} 29 30define i32 @zext_i1_to_i32(i1 %val) { 31 ; CHECK-LABEL: name: zext_i1_to_i32 32 ; CHECK: bb.1 (%ir-block.0): 33 ; CHECK: liveins: $edi 34 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 35 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 36 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1) 37 ; CHECK: $eax = COPY [[ZEXT]](s32) 38 ; CHECK: RET 0, implicit $eax 39 %res = zext i1 %val to i32 40 ret i32 %res 41} 42 43define i64 @zext_i1_to_i64(i1 %val) { 44 ; CHECK-LABEL: name: zext_i1_to_i64 45 ; CHECK: bb.1 (%ir-block.0): 46 ; CHECK: liveins: $edi 47 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 48 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 49 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1) 50 ; CHECK: $rax = COPY [[ZEXT]](s64) 51 ; CHECK: RET 0, implicit $rax 52 %res = zext i1 %val to i64 53 ret i64 %res 54} 55 56define i16 @zext_i8_to_i16(i8 %val) { 57 ; CHECK-LABEL: name: zext_i8_to_i16 58 ; CHECK: bb.1 (%ir-block.0): 59 ; CHECK: liveins: $edi 60 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 61 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 62 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s8) 63 ; CHECK: $ax = COPY [[ZEXT]](s16) 64 ; CHECK: RET 0, implicit $ax 65 %res = zext i8 %val to i16 66 ret i16 %res 67} 68 69define i32 @zext_i8_to_i32(i8 %val) { 70 ; CHECK-LABEL: name: zext_i8_to_i32 71 ; CHECK: bb.1 (%ir-block.0): 72 ; CHECK: liveins: $edi 73 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 74 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 75 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) 76 ; CHECK: $eax = COPY [[ZEXT]](s32) 77 ; CHECK: RET 0, implicit $eax 78 %res = zext i8 %val to i32 79 ret i32 %res 80} 81 82define i64 @zext_i8_to_i64(i8 %val) { 83 ; CHECK-LABEL: name: zext_i8_to_i64 84 ; CHECK: bb.1 (%ir-block.0): 85 ; CHECK: liveins: $edi 86 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 87 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 88 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8) 89 ; CHECK: $rax = COPY [[ZEXT]](s64) 90 ; CHECK: RET 0, implicit $rax 91 %res = zext i8 %val to i64 92 ret i64 %res 93} 94 95define i32 @zext_i16_to_i32(i16 %val) { 96 ; CHECK-LABEL: name: zext_i16_to_i32 97 ; CHECK: bb.1 (%ir-block.0): 98 ; CHECK: liveins: $edi 99 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 100 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) 102 ; CHECK: $eax = COPY [[ZEXT]](s32) 103 ; CHECK: RET 0, implicit $eax 104 %res = zext i16 %val to i32 105 ret i32 %res 106} 107 108define i64 @zext_i16_to_i64(i16 %val) { 109 ; CHECK-LABEL: name: zext_i16_to_i64 110 ; CHECK: bb.1 (%ir-block.0): 111 ; CHECK: liveins: $edi 112 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 113 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 114 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s16) 115 ; CHECK: $rax = COPY [[ZEXT]](s64) 116 ; CHECK: RET 0, implicit $rax 117 %res = zext i16 %val to i64 118 ret i64 %res 119} 120 121define i64 @zext_i32_to_i64(i32 %val) { 122 ; CHECK-LABEL: name: zext_i32_to_i64 123 ; CHECK: bb.1 (%ir-block.0): 124 ; CHECK: liveins: $edi 125 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 126 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) 127 ; CHECK: $rax = COPY [[ZEXT]](s64) 128 ; CHECK: RET 0, implicit $rax 129 %res = zext i32 %val to i64 130 ret i64 %res 131} 132 133define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { 134 ; CHECK-LABEL: name: test_sdiv_i8 135 ; CHECK: bb.1 (%ir-block.0): 136 ; CHECK: liveins: $edi, $esi 137 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 138 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 139 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 140 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 141 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]] 142 ; CHECK: $al = COPY [[SDIV]](s8) 143 ; CHECK: RET 0, implicit $al 144 %res = sdiv i8 %arg1, %arg2 145 ret i8 %res 146} 147 148define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { 149 ; CHECK-LABEL: name: test_sdiv_i16 150 ; CHECK: bb.1 (%ir-block.0): 151 ; CHECK: liveins: $edi, $esi 152 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 153 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 154 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 155 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 156 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]] 157 ; CHECK: $ax = COPY [[SDIV]](s16) 158 ; CHECK: RET 0, implicit $ax 159 %res = sdiv i16 %arg1, %arg2 160 ret i16 %res 161} 162 163define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { 164 ; CHECK-LABEL: name: test_sdiv_i32 165 ; CHECK: bb.1 (%ir-block.0): 166 ; CHECK: liveins: $edi, $esi 167 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 168 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 169 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] 170 ; CHECK: $eax = COPY [[SDIV]](s32) 171 ; CHECK: RET 0, implicit $eax 172 %res = sdiv i32 %arg1, %arg2 173 ret i32 %res 174} 175 176define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { 177 ; CHECK-LABEL: name: test_sdiv_i64 178 ; CHECK: bb.1 (%ir-block.0): 179 ; CHECK: liveins: $rdi, $rsi 180 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 181 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 182 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] 183 ; CHECK: $rax = COPY [[SDIV]](s64) 184 ; CHECK: RET 0, implicit $rax 185 %res = sdiv i64 %arg1, %arg2 186 ret i64 %res 187} 188define float @test_fptrunc(double %in) { 189 ; CHECK-LABEL: name: test_fptrunc 190 ; CHECK: bb.1 (%ir-block.0): 191 ; CHECK: liveins: $xmm0 192 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 193 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) 194 ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[TRUNC]](s64) 195 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPTRUNC]](s32) 196 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) 197 ; CHECK: RET 0, implicit $xmm0 198 %res = fptrunc double %in to float 199 ret float %res 200} 201 202define i8 @test_srem_i8(i8 %arg1, i8 %arg2) { 203 ; CHECK-LABEL: name: test_srem_i8 204 ; CHECK: bb.1 (%ir-block.0): 205 ; CHECK: liveins: $edi, $esi 206 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 207 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 208 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 209 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 210 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]] 211 ; CHECK: $al = COPY [[SREM]](s8) 212 ; CHECK: RET 0, implicit $al 213 %res = srem i8 %arg1, %arg2 214 ret i8 %res 215} 216 217define i16 @test_srem_i16(i16 %arg1, i16 %arg2) { 218 ; CHECK-LABEL: name: test_srem_i16 219 ; CHECK: bb.1 (%ir-block.0): 220 ; CHECK: liveins: $edi, $esi 221 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 222 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 223 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 224 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 225 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]] 226 ; CHECK: $ax = COPY [[SREM]](s16) 227 ; CHECK: RET 0, implicit $ax 228 %res = srem i16 %arg1, %arg2 229 ret i16 %res 230} 231 232define i32 @test_srem_i32(i32 %arg1, i32 %arg2) { 233 ; CHECK-LABEL: name: test_srem_i32 234 ; CHECK: bb.1 (%ir-block.0): 235 ; CHECK: liveins: $edi, $esi 236 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 237 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 238 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] 239 ; CHECK: $eax = COPY [[SREM]](s32) 240 ; CHECK: RET 0, implicit $eax 241 %res = srem i32 %arg1, %arg2 242 ret i32 %res 243} 244 245define i64 @test_srem_i64(i64 %arg1, i64 %arg2) { 246 ; CHECK-LABEL: name: test_srem_i64 247 ; CHECK: bb.1 (%ir-block.0): 248 ; CHECK: liveins: $rdi, $rsi 249 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 250 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 251 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] 252 ; CHECK: $rax = COPY [[SREM]](s64) 253 ; CHECK: RET 0, implicit $rax 254 %res = srem i64 %arg1, %arg2 255 ret i64 %res 256} 257 258define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) { 259 ; CHECK-LABEL: name: test_udiv_i8 260 ; CHECK: bb.1 (%ir-block.0): 261 ; CHECK: liveins: $edi, $esi 262 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 263 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 264 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 265 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 266 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]] 267 ; CHECK: $al = COPY [[UDIV]](s8) 268 ; CHECK: RET 0, implicit $al 269 %res = udiv i8 %arg1, %arg2 270 ret i8 %res 271} 272 273define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) { 274 ; CHECK-LABEL: name: test_udiv_i16 275 ; CHECK: bb.1 (%ir-block.0): 276 ; CHECK: liveins: $edi, $esi 277 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 278 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 279 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 280 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 281 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]] 282 ; CHECK: $ax = COPY [[UDIV]](s16) 283 ; CHECK: RET 0, implicit $ax 284 %res = udiv i16 %arg1, %arg2 285 ret i16 %res 286} 287 288define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) { 289 ; CHECK-LABEL: name: test_udiv_i32 290 ; CHECK: bb.1 (%ir-block.0): 291 ; CHECK: liveins: $edi, $esi 292 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 293 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 294 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]] 295 ; CHECK: $eax = COPY [[UDIV]](s32) 296 ; CHECK: RET 0, implicit $eax 297 %res = udiv i32 %arg1, %arg2 298 ret i32 %res 299} 300 301define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) { 302 ; CHECK-LABEL: name: test_udiv_i64 303 ; CHECK: bb.1 (%ir-block.0): 304 ; CHECK: liveins: $rdi, $rsi 305 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 306 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 307 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]] 308 ; CHECK: $rax = COPY [[UDIV]](s64) 309 ; CHECK: RET 0, implicit $rax 310 %res = udiv i64 %arg1, %arg2 311 ret i64 %res 312} 313 314define i8 @test_urem_i8(i8 %arg1, i8 %arg2) { 315 ; CHECK-LABEL: name: test_urem_i8 316 ; CHECK: bb.1 (%ir-block.0): 317 ; CHECK: liveins: $edi, $esi 318 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 319 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 320 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 321 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 322 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]] 323 ; CHECK: $al = COPY [[UREM]](s8) 324 ; CHECK: RET 0, implicit $al 325 %res = urem i8 %arg1, %arg2 326 ret i8 %res 327} 328 329define i16 @test_urem_i16(i16 %arg1, i16 %arg2) { 330 ; CHECK-LABEL: name: test_urem_i16 331 ; CHECK: bb.1 (%ir-block.0): 332 ; CHECK: liveins: $edi, $esi 333 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 334 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 335 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 336 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 337 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]] 338 ; CHECK: $ax = COPY [[UREM]](s16) 339 ; CHECK: RET 0, implicit $ax 340 %res = urem i16 %arg1, %arg2 341 ret i16 %res 342} 343 344define i32 @test_urem_i32(i32 %arg1, i32 %arg2) { 345 ; CHECK-LABEL: name: test_urem_i32 346 ; CHECK: bb.1 (%ir-block.0): 347 ; CHECK: liveins: $edi, $esi 348 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 349 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 350 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]] 351 ; CHECK: $eax = COPY [[UREM]](s32) 352 ; CHECK: RET 0, implicit $eax 353 %res = urem i32 %arg1, %arg2 354 ret i32 %res 355} 356 357define i64 @test_urem_i64(i64 %arg1, i64 %arg2) { 358 ; CHECK-LABEL: name: test_urem_i64 359 ; CHECK: bb.1 (%ir-block.0): 360 ; CHECK: liveins: $rdi, $rsi 361 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 362 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 363 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]] 364 ; CHECK: $rax = COPY [[UREM]](s64) 365 ; CHECK: RET 0, implicit $rax 366 %res = urem i64 %arg1, %arg2 367 ret i64 %res 368} 369