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/external/libxaac/decoder/armv8/
Dixheaacd_sbr_imdct_using_fft.s177 LD2 {V12.S, V13.S}[0], [X5] , X1
187 LD2 {V12.S, V13.S}[1], [X6] , X1
196 LD2 {V12.S, V13.S}[2], [X7] , X1
205 LD2 {V12.S, V13.S}[3], [X11] , X1
210 ADD V17.4S, V14.4S, V12.4S
214 SUB V16.4S, V14.4S, V12.4S
222 SUB V12.4S, V15.4S, V13.4S
234 ADD V14.4S, V16.4S, V12.4S
235 SUB V10.4S, V16.4S, V12.4S
237 SUB V12.4S, V13.4S, V1.4S
[all …]
Dixheaacd_overlap_add1.s114 UMULL V12.4S, V31.4H, V3.4H
115 USHR V12.4S, V12.4S, #16
116 SMLAL V12.4S, V30.4H, V3.4H
117 SQSHL V12.4S, V12.4S, V11.4S
134 SQSUB V9.4S, V12.4S, V8.4S
155 UMULL V12.4S, V1.4H, V3.4H
159 USHR V12.4S, V12.4S, #16
163 SMLAL V12.4S, V0.4H, V3.4H
167 SQSHL V12.4S, V12.4S, V11.4S
203 SQSUB V9.4S, V12.4S, V8.4S
[all …]
Dixheaacd_overlap_add2.s86 REV64 V12.4H, V14.4H
98 UMLSL V19.4S, V12.4H, V11.4H
122 REV64 V12.4H, V14.4H
144 UMLSL V19.4S, V12.4H, V11.4H
215 LD2 {V12.4H, V13.4H}, [X1], #16
246 UMLSL V19.4S, V12.4H, V10.4H
262 LD2 {V12.4H, V13.4H}, [X1], #16
287 UMLSL V19.4S, V12.4H, V10.4H
/external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/
DContentTypeDetector.java89 case Opcodes.V12: in determineType()
90 case Opcodes.V12 | Opcodes.V_PREVIEW: in determineType()
91 case (Opcodes.V12 + 1): in determineType()
92 case (Opcodes.V12 + 1) | Opcodes.V_PREVIEW: in determineType()
/external/icu/icu4c/source/data/translit/
Dblt_blt_FONIPA.txt46 $V12 = [$V1 $V2 $DIGRAPHS];
47 $V123 = [$V12 $V3];
61 $LO $W? $V12 {($CHK)} → $1 ˧˥; # Tone class 2: High-rising tone
63 $HI $W? $V12 {($CHK)} → $1 ˦; # Tone class 5: High-mid tone
75 $LO $W? $V12 { \uAABF ($F?)} → $1 ˧˥; # Tone class 2: High-rising tone
76 $LO $W? $V12 { \uAAC1 ($F?)} → $1 ˨˩; # Tone class 3: Low-falling tone
77 $HI $W? $V12 { \uAABF ($F?)} → $1 ˦; # Tone class 5: High-mid tone
78 $HI $W? $V12 { \uAAC1 ($F?)} → $1 ˧˩; # Tone class 6: Mid-falling tone
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/instr/
DInstrSupportTest.java59 assertEquals(Opcodes.V12 + 1, version); in classReaderFor_should_read_java_13_class()
68 cw.visit(Opcodes.V12 + 1, 0, "Foo", null, "java/lang/Object", null); in createJava13Class()
129 assertTrue(InstrSupport.needsFrames(Opcodes.V12)); in needFrames_should_return_true_for_versions_greater_than_or_equal_to_1_6()
130 assertTrue(InstrSupport.needsFrames(Opcodes.V12 + 1)); in needFrames_should_return_true_for_versions_greater_than_or_equal_to_1_6()
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Disel-expand-unaligned-loads.ll16 ; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2)
19 ; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])
/external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/
Dfuchsia-multiple-inheritance.cpp127 struct V12 : virtual Static_Base {}; struct
128 struct D7 : V11, V12 {};
/external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/instr/
DInstrSupport.java279 if (originalVersion == Opcodes.V12 + 1) { in classReaderFor()
281 setMajorVersion(Opcodes.V12, b); in classReaderFor()
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/instr/
DClassFileVersionsTest.java28 import static org.objectweb.asm.Opcodes.V12;
114 testVersion(V12, true); in test_12()
119 testVersion(V12 + 1, true); in test_13()
/external/llvm-project/mlir/test/Dialect/SCF/
Dparallel-loop-tiling.mlir31 // CHECK: [[V12:%.*]] = load [[ARG9]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
32 // CHECK: [[V13:%.*]] = addf [[V11]], [[V12]] : f32
106 // CHECK: scf.parallel ([[V12:%.*]], [[V13:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) …
109 // CHECK: = addi [[V15]], [[V12]] : index
/external/llvm-project/llvm/test/Demangle/
Dms-back-references.test68 ?foo_abbb@@YAXV?$A@V?$B@D@N@@V12@V12@@N@@@Z
71 ?foo_abb@@YAXV?$A@DV?$B@D@N@@V12@@N@@@Z
80 ?z_foo@@YA?AVZ@N@@V12@@Z
83 ?b_foo@@YA?AV?$B@D@N@@V12@@Z
86 ?d_foo@@YA?AV?$D@DD@N@@V12@@Z
89 ?abc_foo_abc@@YA?AV?$A@DV?$B@D@N@@V?$C@D@2@@N@@V12@@Z
122 ?qux@PR13207@@YAXV?$K@DV?$I@D@PR13207@@V12@@1@@Z
/external/llvm-project/clang/test/CodeGenObjC/
Dos_log.m50 // CHECK-O0: %[[V12:.*]] = bitcast %{{.*}}** %[[OS_LOG_ARG]] to i8**
51 // CHECK-O0: call void @llvm.objc.storeStrong(i8** %[[V12]], i8* null)
109 // CHECK: %[[V12:.*]] = ptrtoint i8* %[[V11]] to i64
110 // CHECK: call void @__os_log_helper_1_2_2_8_64_8_64(i8* %{{.*}}, i64 %[[V6]], i64 %[[V12]])
Dweak-in-c-struct.m97 // ARM64: %[[V12:.*]] = call i8* @llvm.objc.storeWeak(i8** %[[V7]], i8* %[[V11]])
152 // ARM64: %[[V12:.*]] = call i8* @llvm.objc.storeWeak(i8** %[[V7]], i8* %[[V11]])
Darc-ternary-op.m194 // CHECK: %[[V12:.*]] = load i8*, i8** %[[ARRAYDESTROY_ELEMENT]], align 8
195 // CHECK: call void @llvm.objc.release(i8* %[[V12]])
Dstrong-in-c-struct.m195 // CHECK: %[[V12:.*]] = bitcast i8* %[[V11]] to i8**
199 // CHECK: %[[V16:.*]] = bitcast i8** %[[V12]] to i64*
678 // CHECK: %[[V12:.*]] = load i16, i16* %[[V11]], align 8
679 // CHECK: store i16 %[[V12]], i16* %[[V10]], align 8
725 // CHECK: %[[V12:.*]] = bitcast i8** %[[ADDR_CUR]] to i32*
728 // CHECK: store volatile i32 %[[V14]], i32* %[[V12]], align 4
/external/llvm-project/clang/test/CodeGenObjCXX/
Darc-blocks.mm88 // CHECK: %[[V12:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*…
89 // CHECK: invoke void @_ZN5test12S0C1ERKS0_(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V12]], %[[STRUCT_TES…
105 // CHECK: invoke void @_ZN5test12S0D1Ev(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V12]])
236 // CHECK: %[[V12:.*]] = bitcast i8* %[[V11]] to void ()*
237 // CHECK: store void ()* %[[V12]], void ()** %[[B1]], align 8
281 // CHECK: %[[V12:.*]] = bitcast i8* %[[V11]] to void ()*
282 // CHECK: store void ()* %[[V12]], void ()** %[[B1]], align 8
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td86 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
100 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
/external/llvm/test/Instrumentation/SanitizerCoverage/
Dcoverage.ll88 ; CHECK-8BIT: [[V12:%[0-9]*]] = add i8 [[V11]], 1
89 ; CHECK-8BIT: store i8 [[V12]]{{.*}}!nosanitize
/external/llvm-project/llvm/test/Bitcode/
Dupgrade-arc-runtime-calls.ll81 // ARC-NEXT: %[[V12:.*]] = tail call i8* @llvm.objc.unsafeClaimAutoreleasedReturnValue(i8* %[[A]])
114 // NOUPGRADE-NEXT: %[[V12:.*]] = tail call i8* @objc_unsafeClaimAutoreleasedReturnValue(i8* %[[A]])
/external/libchrome/mojo/public/interfaces/bindings/tests/
Dtest_structs.mojom210 const int32 V12 = 0;
235 int32 f12 = V12;
/external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/
Dsmlad11.ll16 ; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[ACC]])
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
DHexagonRegisterInfo.td189 def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>;
275 V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,

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