1//===- HexagonCallingConv.td ----------------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class CCIfArgIsVarArg<CCAction A> 10 : CCIf<"State.isVarArg() && " 11 "ValNo >= static_cast<HexagonCCState&>(State)" 12 ".getNumNamedVarArgParams()", A>; 13 14def CC_HexagonStack: CallingConv<[ 15 CCIfType<[i32,v2i16,v4i8], 16 CCAssignToStack<4,4>>, 17 CCIfType<[i64,v2i32,v4i16,v8i8], 18 CCAssignToStack<8,8>> 19]>; 20 21def CC_Hexagon: CallingConv<[ 22 CCIfType<[i1,i8,i16], 23 CCPromoteToType<i32>>, 24 CCIfType<[f32], 25 CCBitConvertToType<i32>>, 26 CCIfType<[f64], 27 CCBitConvertToType<i64>>, 28 29 CCIfByVal< 30 CCPassByVal<8,8>>, 31 CCIfArgIsVarArg< 32 CCDelegateTo<CC_HexagonStack>>, 33 34 // Pass split values in pairs, allocate odd register if necessary. 35 CCIfType<[i32], 36 CCIfSplit< 37 CCCustom<"CC_SkipOdd">>>, 38 39 CCIfType<[i32,v2i16,v4i8], 40 CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>, 41 // Make sure to allocate any skipped 32-bit register, so it does not get 42 // allocated to a subsequent 32-bit value. 43 CCIfType<[i64,v2i32,v4i16,v8i8], 44 CCCustom<"CC_SkipOdd">>, 45 CCIfType<[i64,v2i32,v4i16,v8i8], 46 CCAssignToReg<[D0,D1,D2]>>, 47 48 CCDelegateTo<CC_HexagonStack> 49]>; 50 51def RetCC_Hexagon: CallingConv<[ 52 CCIfType<[i1,i8,i16], 53 CCPromoteToType<i32>>, 54 CCIfType<[f32], 55 CCBitConvertToType<i32>>, 56 CCIfType<[f64], 57 CCBitConvertToType<i64>>, 58 59 // Small structures are returned in a pair of registers, (which is 60 // always r1:0). In such case, what is returned are two i32 values 61 // without any additional information (in ArgFlags) stating that 62 // they are parts of a structure. Because of that there is no way 63 // to differentiate that situation from an attempt to return two 64 // values, so always assign R0 and R1. 65 CCIfSplit< 66 CCAssignToReg<[R0,R1]>>, 67 CCIfType<[i32,v2i16,v4i8], 68 CCAssignToReg<[R0,R1]>>, 69 CCIfType<[i64,v2i32,v4i16,v8i8], 70 CCAssignToReg<[D0]>> 71]>; 72 73 74class CCIfHvx64<CCAction A> 75 : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()" 76 ".useHVX64BOps()", A>; 77 78class CCIfHvx128<CCAction A> 79 : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()" 80 ".useHVX128BOps()", A>; 81 82def CC_Hexagon_HVX: CallingConv<[ 83 // HVX 64-byte mode 84 CCIfHvx64< 85 CCIfType<[v16i32,v32i16,v64i8], 86 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>, 87 CCIfHvx64< 88 CCIfType<[v32i32,v64i16,v128i8], 89 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>, 90 CCIfHvx64< 91 CCIfType<[v16i32,v32i16,v64i8], 92 CCAssignToStack<64,64>>>, 93 CCIfHvx64< 94 CCIfType<[v32i32,v64i16,v128i8], 95 CCAssignToStack<128,64>>>, 96 97 // HVX 128-byte mode 98 CCIfHvx128< 99 CCIfType<[v32i32,v64i16,v128i8], 100 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>, 101 CCIfHvx128< 102 CCIfType<[v64i32,v128i16,v256i8], 103 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>, 104 CCIfHvx128< 105 CCIfType<[v32i32,v64i16,v128i8], 106 CCAssignToStack<128,128>>>, 107 CCIfHvx128< 108 CCIfType<[v64i32,v128i16,v256i8], 109 CCAssignToStack<256,128>>>, 110 111 CCDelegateTo<CC_Hexagon> 112]>; 113 114def RetCC_Hexagon_HVX: CallingConv<[ 115 // HVX 64-byte mode 116 CCIfHvx64< 117 CCIfType<[v16i32,v32i16,v64i8], 118 CCAssignToReg<[V0]>>>, 119 CCIfHvx64< 120 CCIfType<[v32i32,v64i16,v128i8], 121 CCAssignToReg<[W0]>>>, 122 123 // HVX 128-byte mode 124 CCIfHvx128< 125 CCIfType<[v32i32,v64i16,v128i8], 126 CCAssignToReg<[V0]>>>, 127 CCIfHvx128< 128 CCIfType<[v64i32,v128i16,v256i8], 129 CCAssignToReg<[W0]>>>, 130 131 CCDelegateTo<RetCC_Hexagon> 132]>; 133 134