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Searched refs:V20 (Results 1 – 25 of 39) sorted by relevance

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/external/libxaac/decoder/armv8/
Dixheaacd_no_lap1.s84 SSHR V20.4S, V21.4S, #16
85 REV64 V20.4S, V20.4S
89 UZP1 V27.8H, V20.8H, V20.8H
112 SSHR V20.4S, V21.4S, #16
114 REV64 V20.4S, V20.4S
116 UZP1 V27.8H, V20.8H, V20.8H
Dixheaacd_overlap_add2.s71 DUP V20.4S, W4
88 SQADD V22.4S, V23.4S, V20.4S
121 SQADD V18.4S, V19.4S, V20.4S
124 SQADD V22.4S, V23.4S, V20.4S
158 SQADD V18.4S, V19.4S, V20.4S
203 SQADD V22.4S, V23.4S, V20.4S
224 SQADD V22.4S, V23.4S, V20.4S
266 SQADD V18.4S, V19.4S, V20.4S
271 SQADD V22.4S, V23.4S, V20.4S
295 SQADD V18.4S, V19.4S, V20.4S
Dixheaacd_sbr_imdct_using_fft.s295 ADD V20.4S, V3.4S, V19.4S
340 TRN1 V12.4S, V4.4S, V20.4S
341 TRN2 V22.4S, V4.4S, V20.4S
491 SUB V20.4S, V0.4S, V8.4S
509 ADD V8.4S, V20.4S, V30.4S
512 SUB V12.4S, V20.4S, V30.4S
600 LD2 {V20.H, V21.H}[0], [X9], X2
606 LD2 {V20.H, V21.H}[1], [X10], X11
612 LD2 {V20.H, V21.H}[2], [X9], X2
618 LD2 {V20.H, V21.H}[3], [X10], X11
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-move-21.ll25 %V20 = shufflevector <2 x double> %V19, <2 x double> undef, <2 x i32> zeroinitializer
28 %V23 = fmul <2 x double> %V20, %V22
/external/opencensus-java/api/src/test/java/io/opencensus/stats/
DViewDataTest.java223 createView(DISTRIBUTION), ImmutableMap.of(Arrays.asList(V10, V20), CountData.create(100))); in preventAggregationAndAggregationDataMismatch_Distribution_Count()
275 private static final TagValue V20 = TagValue.create("v20"); field in ViewDataTest
289 Arrays.asList(V10, V20),
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-64b.ll21 ; CHECK: v[[V20:[0-9]+]].h = vpopcount(v0.h)
22 ; CHECK: v[[V21:[0-9]+]]:[[V22:[0-9]+]].uw = vzxt(v[[V20]].uh)
Dbitcount-128b.ll21 ; CHECK: v[[V20:[0-9]+]].h = vpopcount(v0.h)
22 ; CHECK: v[[V21:[0-9]+]]:[[V22:[0-9]+]].uw = vzxt(v[[V20]].uh)
/external/llvm-project/llvm/test/Transforms/InstCombine/X86/
Dx86-vec_demanded_elts.ll34 ; CHECK-NEXT: [[V20:%.*]] = insertelement <4 x float> undef, float %f, i32 0
35 ; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[V20]])
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp71 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
DHexagonRegisterInfo.td193 def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>;
275 V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp107 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
/external/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp108 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp108 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc191 V20 = 171,
1566 …PC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
1596 …PC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2487 { PPC::V20, 97U },
2762 { PPC::V20, 97U },
3040 { PPC::V20, 97U },
3315 { PPC::V20, 97U },
5740 …PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22…
5742 …PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22…
5748 static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24,…
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
DHexagonRegisterInfo.td217 def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>;
237 def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td77 CCIfFixed<CCAssignToReg<[V16, V17, V18, V19, V20, V21]>>>>,
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td77 CCIfFixed<CCAssignToReg<[V16, V17, V18, V19, V20, V21]>>>>,
/external/llvm-project/mlir/test/Dialect/LLVMIR/
Droundtrip.mlir179 // CHECK: %[[V20:.*]] = llvm.insertvalue %[[V18]], %[[V19]][0] : !llvm.struct<(i32, double, i32)>
180 // CHECK: %[[V21:.*]] = llvm.insertvalue %[[V7]], %[[V20]][1] : !llvm.struct<(i32, double, i32)>
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
176 {PPC::V20, -192}}; in getCalleeSavedSpillSlots()
234 {PPC::V20, -192}}; in getCalleeSavedSpillSlots()
DPPCCallingConv.td219 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
DPPCRegisterInfo.td294 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp98 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
193 {PPC::V20, -192}, in getCalleeSavedSpillSlots()
271 {PPC::V20, -192}}; in getCalleeSavedSpillSlots()

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