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Searched refs:VAL0 (Results 1 – 25 of 49) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Damdgcn-ieee.ll4 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
6 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
19 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
21 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
34 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
36 ; GCN-NOT: [[VAL0]]
38 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
49 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
51 ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
64 ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
[all …]
Dds_write2st64.ll30 ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
33 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]$}}
38 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
59 ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
62 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}{{$}}
67 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
87 ; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9…
90 ; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]$}}
95 ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
Dpack.v2i16.ll7 ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
9 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
40 ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
41 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1c8
55 ; GFX9: global_load_dword [[VAL0:v[0-9]+]]
58 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
78 ; GFX9: global_load_dword [[VAL0:v[0-9]+]]
81 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
142 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]]
145 ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[K]], 16, [[VAL0]]
Dpack.v2f16.ll7 ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
9 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
43 ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
44 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1234
59 ; GFX9: global_load_dword [[VAL0:v[0-9]+]]
62 ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VAL0]]
84 ; GFX9: global_load_dword [[VAL0:v[0-9]+]]
87 ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VAL0]]
152 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]]
155 ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]]
Dfminnum.f64.ll42 ; GCN: ds_read_b64 [[VAL0:v\[[0-9]+:[0-9]+\]]]
44 ; GCN-NOT: [[VAL0]]
46 ; GCN: v_min_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VAL0]], [[VAL1]]
Dsminmax.v2i16.ll109 ; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c
110 ; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]]
112 ; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]]
134 ; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
136 ; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]]
137 ; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]]
Dsminmax.ll199 ; GCN: s_load_dword [[VAL0:s[0-9]+]]
202 ; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
203 ; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
215 ; GCN: {{buffer|flat|global}}_load_dword [[VAL0:v[0-9]+]]
218 ; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]
219 ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]
/external/llvm-project/llvm/test/Transforms/EarlyCSE/
Dinvariant-loads.ll10 ; NO_ASSUME-NEXT: [[VAL0:%.*]] = load i32, i32* [[PTR:%.*]], align 4, !invariant.load !0
11 ; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
12 ; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
13 ; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
17 ; USE_ASSUME-NEXT: [[VAL0:%.*]] = load i32, i32* [[PTR:%.*]], align 4, !invariant.load !0
18 ; USE_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
20 ; USE_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
21 ; USE_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
37 ; NO_ASSUME-NEXT: [[VAL0:%.*]] = load i32, i32* [[PTR:%.*]], align 4, !invariant.load !0
38 ; NO_ASSUME-NEXT: call void @clobber_and_use(i32 [[VAL0]])
[all …]
/external/llvm-project/llvm/test/Transforms/Scalarizer/
Dvariable-extractelement.ll35 ; DEFAULT-NEXT: [[VAL0:%.*]] = load <4 x i32>, <4 x i32>* [[SRC:%.*]], align 16
36 ; DEFAULT-NEXT: [[VAL0_I0:%.*]] = extractelement <4 x i32> [[VAL0]], i32 0
38 ; DEFAULT-NEXT: [[VAL0_I1:%.*]] = extractelement <4 x i32> [[VAL0]], i32 1
40 ; DEFAULT-NEXT: [[VAL0_I2:%.*]] = extractelement <4 x i32> [[VAL0]], i32 2
42 ; DEFAULT-NEXT: [[VAL0_I3:%.*]] = extractelement <4 x i32> [[VAL0]], i32 3
55 ; OFF-NEXT: [[VAL0:%.*]] = load <4 x i32>, <4 x i32>* [[SRC:%.*]], align 16
56 ; OFF-NEXT: [[VAL0_I0:%.*]] = extractelement <4 x i32> [[VAL0]], i32 0
58 ; OFF-NEXT: [[VAL0_I1:%.*]] = extractelement <4 x i32> [[VAL0]], i32 1
60 ; OFF-NEXT: [[VAL0_I2:%.*]] = extractelement <4 x i32> [[VAL0]], i32 2
62 ; OFF-NEXT: [[VAL0_I3:%.*]] = extractelement <4 x i32> [[VAL0]], i32 3
Dvariable-insertelement.ll39 ; DEFAULT-NEXT: [[VAL0:%.*]] = load <4 x i32>, <4 x i32>* [[SRC:%.*]], align 16
41 ; DEFAULT-NEXT: [[VAL0_I0:%.*]] = extractelement <4 x i32> [[VAL0]], i32 0
44 ; DEFAULT-NEXT: [[VAL0_I1:%.*]] = extractelement <4 x i32> [[VAL0]], i32 1
47 ; DEFAULT-NEXT: [[VAL0_I2:%.*]] = extractelement <4 x i32> [[VAL0]], i32 2
50 ; DEFAULT-NEXT: [[VAL0_I3:%.*]] = extractelement <4 x i32> [[VAL0]], i32 3
64 ; OFF-NEXT: [[VAL0:%.*]] = load <4 x i32>, <4 x i32>* [[SRC:%.*]], align 16
65 ; OFF-NEXT: [[VAL1:%.*]] = insertelement <4 x i32> [[VAL0]], i32 1, i32 [[INDEX:%.*]]
/external/tensorflow/tensorflow/compiler/mlir/hlo/tests/
Dlower-complex.mlir8 // CHECK-DAG: [[VAL0:%.+]] = mhlo.add %arg0, %arg2
14 // CHECK: return [[VAL0]], [[VAL1]]
23 // CHECK-DAG: [[VAL0:%.+]] = mhlo.add %arg0, %arg2
29 // CHECK: return [[VAL0]], [[VAL1]]
38 // CHECK-DAG: [[VAL0:%.+]] = mhlo.subtract %arg0, %arg2
44 // CHECK: return [[VAL0]], [[VAL1]]
53 // CHECK-DAG: [[VAL0:%.+]] = mhlo.subtract %arg0, %arg2
59 // CHECK: return [[VAL0]], [[VAL1]]
68 // CHECK-DAG: [[VAL0:%.+]] = mhlo.multiply %arg0, %arg2
70 // CHECK-DAG: [[VAL2:%.+]] = mhlo.subtract [[VAL0]], [[VAL1]]
[all …]
Dlegalize-control-flow.mlir6 //CHECK: ^bb1([[VAL0:%.+]]: tensor<i64>):
7 //CHECK: [[VAL1:%.+]] = "mhlo.compare"([[VAL0]], [[VAL0]])
9 //CHECK: cond_br [[VAL2]], ^bb2([[VAL0]] : tensor<i64>), ^bb3([[VAL0]] : tensor<i64>)
33 …// CHECK: [[VAL0:%.+]] = "mhlo.compare"(%arg0, [[C0]]) {comparison_direction = "LT"} : (tensor<f…
36 // CHECK: [[VAL1:%.+]] = tensor.extract [[VAL0]][] : tensor<i1>
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/translate/
Dif.mlir6 // CHECK: %[[VAL0:.+]] = f32[] get-tuple-element((f32[]) %[[A0]]), index=0
9 // CHECK: %[[VAL1:.+]] = f32[] log(f32[] %[[VAL0]])
20 // CHECK: %[[VAL0:.+]] = f32[] get-tuple-element((f32[]) %[[A0]]), index=0
23 // CHECK: %[[VAL1:.+]] = f32[] exponential(f32[] %[[VAL0]])
34 // CHECK: %[[VAL0:.+]] = f32[] constant(10)
37 // CHECK: %[[VAL1:.+]] = pred[] compare(f32[] %[[A0]], f32[] %[[VAL0]]), direction=LT
/external/llvm-project/mlir/test/Dialect/Linalg/
Dsparse_storage.mlir35 // CHECK-TYPE0: %[[VAL0:.*]] = load %{{.*}}[%[[I]]] : memref<?xf64>
37 // CHECK-TYPE0: %[[MUL:.*]] = mulf %[[VAL0]], %[[VAL1]] : f64
51 // CHECK-TYPE1: %[[VAL0:.*]] = load %{{.*}}[%[[I]]] : memref<?xf64>
53 // CHECK-TYPE1: %[[MUL:.*]] = mulf %[[VAL0]], %[[VAL1]] : f64
67 // CHECK-TYPE2: %[[VAL0:.*]] = load %{{.*}}[%[[I]]] : memref<?xf64>
69 // CHECK-TYPE2: %[[MUL:.*]] = mulf %[[VAL0]], %[[VAL1]] : f64
83 // CHECK-TYPE3: %[[VAL0:.*]] = load %{{.*}}[%[[I]]] : memref<?xf64>
85 // CHECK-TYPE3: %[[MUL:.*]] = mulf %[[VAL0]], %[[VAL1]] : f64
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/
Dlegalize-tf-control-flow.mlir6 …// CHECK: [[VAL0:%.+]] = "mhlo.compare"([[ARG0]], [[ARG1]]) {comparison_direction = "GT"} : (tenso…
9 // CHECK: [[VAL2:%.+]] = "mhlo.if"([[VAL0]], [[VAL1]], [[VAL1]]) ( {
47 // CHECK: [[VAL0:%.+]] = "mhlo.compare"([[ARG0]], [[ARG1]]) {comparison_direction = "GT"}
51 // CHECK: [[VAL3:%.+]] = "mhlo.if"([[VAL0]], [[VAL1]], [[VAL2]]) ( {
123 // CHECK: [[VAL0:%.+]] = "mhlo.tuple"([[ARG1]])
126 // CHECK: [[VAL3:%.+]]:2 = "mhlo.case"([[BRANCH_INDEX]], [[VAL0]], [[VAL1]], [[VAL2]]) ( {
159 // CHECK: [[VAL0:%.+]] = mhlo.constant dense<0>
163 // CHECK: [[VAL2:%.+]] = "mhlo.tuple"([[VAL0]], [[VAL1]], [[VAL0]])
202 // CHECK: [[VAL0:%.+]] = mhlo.constant dense<0>
206 // CHECK: [[VAL2:%.+]] = "mhlo.tuple"([[VAL0]], [[VAL1]], [[VAL0]])
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dds_write2.ll25 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
84 ; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}}
87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
106 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
125 ; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
144 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
147 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
[all …]
Dds_write2st64.ll23 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
26 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
44 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
47 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
64 ; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9…
67 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
Dsminmax.ll154 ; GCN: s_load_dword [[VAL0:s[0-9]+]]
157 ; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
158 ; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
170 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]]
173 ; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]]
174 ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]]
Dctpop.ll42 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
44 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
45 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
62 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
64 ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
/external/angle/third_party/vulkan-deps/glslang/src/Test/
DcppComplexExpr.vert105 #define VAL0 0
123 #if VAL0 || UNDEF // UNDEF ERROR
126 #if VAL0 && UNDEF
153 #if VAL0 || UNDEF && UNDEF2 // UNDEF ERROR
159 #if (VAL0 && UNDEF) || UNDEF2 // UNDEF2 ERROR
/external/deqp-deps/glslang/Test/
DcppComplexExpr.vert105 #define VAL0 0
123 #if VAL0 || UNDEF // UNDEF ERROR
126 #if VAL0 && UNDEF
153 #if VAL0 || UNDEF && UNDEF2 // UNDEF ERROR
159 #if (VAL0 && UNDEF) || UNDEF2 // UNDEF2 ERROR
/external/llvm-project/mlir/test/Transforms/
Dcanonicalize-dce.mlir97 // CHECK-NEXT: [[VAL0:%.+]] = addf %arg0, %arg0 : f32
98 // CHECK-NEXT: return [[VAL0]] : f32
141 // CHECK-NEXT: ^bb1([[VAL0:%.+]]: tensor<2xf32>, [[VAL1:%.+]]: tensor<4xf32>):
142 // CHECK-NEXT: "foo.print"([[VAL0]])
Dscf-loop-utils.mlir28 …// CHECK: %[[RES:.*]]:2 = scf.for %[[I:.*]] = %[[lb]] to %[[ub]] step %[[step]] iter_args(%[[VAL0:…
30 // CHECK: scf.yield %[[VAL0]], %[[YIELD]] : f32, index
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/X86/
Dmerge-cond-stores-cost.ll10 ; CHECK-NEXT: [[VAL0:%.*]] = sdiv i32 [[D:%.*]], [[C:%.*]]
11 ; CHECK-NEXT: store i32 [[VAL0]], i32* [[P:%.*]]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsibling-call.ll76 ; CHECK: ldr [[VAL0:x[0-9]+]],
78 ; CHECK: str [[VAL0]],

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