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Searched refs:VCTP (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLowOverheadLoops.cpp130 MachineInstr *VCTP = nullptr; member
153 return !Revert && FoundAllComponents() && VCTP && in IsTailPredicationLegal()
181 VCTP->getOperand(1) : Start->getOperand(0); in getCount()
189 return VCTPOpcodeToLSTP(VCTP->getOpcode(), IsDo); in getStartOpcode()
196 if (VCTP) dbgs() << "ARM Loops: Found VCTP: " << *VCTP; in dump()
328 assert(VCTP && "VCTP instruction expected but is not set"); in ValidateTailPredicate()
333 if (Block.IsPredicatedOn(VCTP)) in ValidateTailPredicate()
342 if (PredMI.Predicates.count(VCTP) || isVCTP(PredMI.MI)) in ValidateTailPredicate()
357 Register NumElements = VCTP->getOperand(1).getReg(); in ValidateTailPredicate()
362 if (RDA->getReachingDef(VCTP, NumElements) >= 0) { in ValidateTailPredicate()
[all …]
DMVETailPredication.cpp490 Function *VCTP = Intrinsic::getDeclaration(M, VCTPID); in InsertVCTPIntrinsic() local
491 Value *TailPredicate = Builder.CreateCall(VCTP, Processed); in InsertVCTPIntrinsic()
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dvector-reduce-mve-tail.ll12 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELTS]])
14 ; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]]
15 ; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]],
18 ; CHECK: [[VPSEL:%[^ ]+]] = select <4 x i1> [[VCTP]],
Dtail-pred-basic.ll8 ; CHECK: [[VCTP:%[^ ]+]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 [[ELEMS]])
10 … i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* {{.*}}, i32 4, <16 x i1> [[VCTP]], <16 x i8> undef)
11 … i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* {{.*}}, i32 4, <16 x i1> [[VCTP]], <16 x i8> undef)
12 …id @llvm.masked.store.v16i8.p0v16i8(<16 x i8> {{.*}}, <16 x i8>* {{.*}}, i32 4, <16 x i1> [[VCTP]])
65 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[ELEMS]])
67 … i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]], <8 x i16> undef)
68 … i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]], <8 x i16> undef)
69 …oid @llvm.masked.store.v8i16.p0v8i16(<8 x i16> {{.*}}, <8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]])
121 ; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELEMS]])
123 … i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{.*}}, i32 4, <4 x i1> [[VCTP]], <4 x i32> undef)
[all …]
Dtail-pred-reduce.ll8 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[PHI]])
10 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp4, i32 4, <8 x i1> [[VCTP]],…
11 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp6, i32 4, <8 x i1> [[VCTP]],…
78 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[PHI]])
80 ; CHECK: call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp4, i32 4, <8 x i1> [[VCTP]],…
Dlsr-profitable-chain.ll7 ; Tests that LSR will not interfere with the VCTP intrinsic,
Dtail-pred-widen.ll56 ; CHECK: [[VCTP:%[^ ]+]] = call <8 x i1> @llvm.arm.mve.vctp16(i32 [[ELEMS]])
58 … i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* {{.*}}, i32 4, <8 x i1> [[VCTP]], <8 x i16> undef)
Dvpt-blocks.mir360 ; VCTP's.
490 …ts that secondary VCTPs are refused when their operand is not the same register as the main VCTP's.
610 ; Test including a else-predicated VCTP.
962 ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP.
Dwrong-vctp-operand-liveout.mir4 # The VCTP uses r2, which is redefined in the loop.
Div-two-vcmp-reordered.mir4 # TODO: We should be able to handle the VCMP -> VPST -> VCMP -> VCTP case.
/external/llvm-project/llvm/lib/Target/ARM/
DMVEVPTOptimisationsPass.cpp215 for (MachineInstr *VCTP : VCTPs) { in ConvertTailPredLoop()
216 LLVM_DEBUG(dbgs() << " with VCTP " << *VCTP); in ConvertTailPredLoop()
217 if (VCTP->getOpcode() != FirstVCTP->getOpcode() || in ConvertTailPredLoop()
218 VCTP->getOperand(0).getReg() != FirstVCTP->getOperand(0).getReg()) { in ConvertTailPredLoop()
DMVETailPredication.cpp378 Function *VCTP = Intrinsic::getDeclaration(M, VCTPID); in InsertVCTPIntrinsic() local
379 Value *VCTPCall = Builder.CreateCall(VCTP, Processed); in InsertVCTPIntrinsic()
DARMLowOverheadLoops.cpp647 MachineInstr *VCTP = VCTPs.back(); in ValidateTailPredicate() local
653 TPNumElements = VCTP->getOperand(1); in ValidateTailPredicate()
659 if (RDA.hasLocalDefBefore(VCTP, NumElements)) { in ValidateTailPredicate()
754 MachineBasicBlock *MBB = VCTP->getParent(); in ValidateTailPredicate()
760 &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) { in ValidateTailPredicate()
763 unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode()); in ValidateTailPredicate()