/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | legalize-reduce-fadd.mir | 14 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>) 15 ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32) 33 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s64) = G_VECREDUCE_FADD [[COPY]](<2 x s64>) 34 ; CHECK: $x0 = COPY [[VECREDUCE_FADD]](s64)
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D | regbankselect-reductions.mir | 15 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>) 16 ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32)
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D | irtranslator-reductions.ll | 26 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[COPY1]](<4 x s32>) 27 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 931 VECREDUCE_FADD, VECREDUCE_FMUL, enumerator
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/external/llvm-project/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 1142 VECREDUCE_FADD, enumerator
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 484 case ISD::VECREDUCE_FADD: in LegalizeOp() 880 case ISD::VECREDUCE_FADD: in Expand()
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D | SelectionDAGDumper.cpp | 457 case ISD::VECREDUCE_FADD: return "vecreduce_fadd"; in getOperationName()
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D | LegalizeFloatTypes.cpp | 137 case ISD::VECREDUCE_FADD: in SoftenFloatResult() 2258 case ISD::VECREDUCE_FADD: in PromoteFloatResult() 2621 case ISD::VECREDUCE_FADD: in SoftPromoteHalfResult()
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D | LegalizeVectorTypes.cpp | 616 case ISD::VECREDUCE_FADD: in ScalarizeVectorOperand() 2117 case ISD::VECREDUCE_FADD: in SplitVectorOperand() 4389 case ISD::VECREDUCE_FADD: in WidenVectorOperand()
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D | LegalizeDAG.cpp | 1164 case ISD::VECREDUCE_FADD: in LegalizeOp() 3937 case ISD::VECREDUCE_FADD: in ExpandNode()
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D | SelectionDAG.cpp | 349 case ISD::VECREDUCE_FADD: in getVecReduceBaseOpcode()
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D | SelectionDAGBuilder.cpp | 9038 DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), in visitVectorReduce()
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D | DAGCombiner.cpp | 1736 case ISD::VECREDUCE_FADD: in visit()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 436 case ISD::VECREDUCE_FADD: return "vecreduce_fadd"; in getOperationName()
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D | LegalizeVectorOps.cpp | 483 case ISD::VECREDUCE_FADD: in LegalizeOp() 987 case ISD::VECREDUCE_FADD: in Expand()
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D | LegalizeVectorTypes.cpp | 604 case ISD::VECREDUCE_FADD: in ScalarizeVectorOperand() 1984 case ISD::VECREDUCE_FADD: in SplitVectorOperand() 2070 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break; in SplitVecOp_VECREDUCE() 4225 case ISD::VECREDUCE_FADD: in WidenVectorOperand() 4711 case ISD::VECREDUCE_FADD: in WidenVecOp_VECREDUCE()
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D | LegalizeDAG.cpp | 1148 case ISD::VECREDUCE_FADD: in LegalizeOp() 3797 case ISD::VECREDUCE_FADD: in ExpandNode()
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D | TargetLowering.cpp | 7611 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break; in expandVecReduce()
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D | SelectionDAGBuilder.cpp | 8969 DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2)); in visitVectorReduce()
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D | DAGCombiner.cpp | 1613 case ISD::VECREDUCE_FADD: in visit()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 712 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); in initActions()
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/external/llvm-project/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 830 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); in initActions()
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 1227 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in AArch64TargetLowering() 1364 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in addTypeForFixedLengthSVE() 4290 case ISD::VECREDUCE_FADD: in LowerOperation() 10209 Op.getOpcode() == ISD::VECREDUCE_FADD || in LowerVECREDUCE() 10235 case ISD::VECREDUCE_FADD: in LowerVECREDUCE()
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in addMVEVectorTypes() 379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom); in addMVEVectorTypes() 383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom); in addMVEVectorTypes() 9531 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break; in LowerVecReduce() 9804 case ISD::VECREDUCE_FADD: in LowerOperation()
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