1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s 3 4--- 5name: fadd_v2s32 6legalized: true 7tracksRegLiveness: true 8body: | 9 bb.1: 10 liveins: $d0 11 12 ; CHECK-LABEL: name: fadd_v2s32 13 ; CHECK: liveins: $d0 14 ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 15 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>) 16 ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32) 17 ; CHECK: RET_ReallyLR implicit $w0 18 %0:_(<2 x s32>) = COPY $d0 19 %1:_(s32) = G_VECREDUCE_FADD %0(<2 x s32>) 20 $w0 = COPY %1(s32) 21 RET_ReallyLR implicit $w0 22 23... 24--- 25name: add_v4s32 26legalized: true 27tracksRegLiveness: true 28body: | 29 bb.1: 30 liveins: $q0 31 32 ; CHECK-LABEL: name: add_v4s32 33 ; CHECK: liveins: $q0 34 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 35 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>) 36 ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32) 37 ; CHECK: RET_ReallyLR implicit $w0 38 %0:_(<4 x s32>) = COPY $q0 39 %1:_(s32) = G_VECREDUCE_ADD %0(<4 x s32>) 40 $w0 = COPY %1(s32) 41 RET_ReallyLR implicit $w0 42 43... 44