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Searched refs:VMOVDRR (Results 1 – 25 of 45) sorted by relevance

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/external/llvm-project/llvm/test/DebugInfo/MIR/ARM/
Dsplit-superreg-piece.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
Dsplit-superreg.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
Dsplit-superreg-complex.mir114 $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19
115 …$d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location…
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1008 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1085 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1115 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1118 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1121 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1124 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2292 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
DARMISelLowering.h77 VMOVDRR, // Two gprs to double. enumerator
DARM.td125 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
DARMISelLowering.cpp1152 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
1486 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1503 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
3108 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
3716 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
4250 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4321 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
4479 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
9618 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP()) in PerformVMOVRRDCombine()
10328 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
[all …]
DARMScheduleSwift.td629 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td26 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1094 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1178 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1210 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1213 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1216 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1219 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2626 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
DARMISelLowering.h111 VMOVDRR, // Two gprs to double. enumerator
DARMInstructionSelector.cpp258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
DARMISelLowering.cpp1590 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
1998 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2015 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
3900 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
4716 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
5508 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
5579 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
5807 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
6590 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
12744 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
[all …]
DARM.td223 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
DARMScheduleSwift.td641 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
DARMScheduleA57.td811 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td26 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1163 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1247 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1279 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1282 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1285 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1288 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2727 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
DARMISelLowering.h113 VMOVDRR, // Two gprs to double. enumerator
DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
DARMExpandPseudoInsts.cpp1136 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1299 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1487 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
DARMISelLowering.cpp1652 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; in getTargetNodeName()
2127 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2144 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
4125 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
4994 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
5755 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
5826 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
5996 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
6791 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
13565 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
[all …]
DARMScheduleSwift.td641 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
DARM.td223 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
DARMScheduleA57.td808 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/
Dselect-fp.mir858 ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dvaddv.mir1854 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
1899 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2107 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2152 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2360 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2405 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…
2613 …; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $n…
2658 …renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, impli…

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