1# RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- | 4 define void @test_trunc_s64() { ret void } 5 6 define void @test_fadd_s32() { ret void } 7 define void @test_fadd_s64() { ret void } 8 9 define void @test_fsub_s32() { ret void } 10 define void @test_fsub_s64() { ret void } 11 12 define void @test_fmul_s32() { ret void } 13 define void @test_fmul_s64() { ret void } 14 15 define void @test_fdiv_s32() { ret void } 16 define void @test_fdiv_s64() { ret void } 17 18 define void @test_fneg_s32() { ret void } 19 define void @test_fneg_s64() { ret void } 20 21 define void @test_fma_s32() { ret void } 22 define void @test_fma_s64() { ret void } 23 24 define void @test_fpext_s32_to_s64() { ret void } 25 define void @test_fptrunc_s64_to_s32() {ret void } 26 27 define void @test_fptosi_s32() { ret void } 28 define void @test_fptosi_s64() { ret void } 29 define void @test_fptoui_s32() { ret void } 30 define void @test_fptoui_s64() { ret void } 31 32 define void @test_sitofp_s32() { ret void } 33 define void @test_sitofp_s64() { ret void } 34 define void @test_uitofp_s32() { ret void } 35 define void @test_uitofp_s64() { ret void } 36 37 define void @test_load_f32() { ret void } 38 define void @test_load_f64() { ret void } 39 40 define void @test_stores() { ret void } 41 42 define void @test_phi_s64() { ret void } 43 44 define void @test_soft_fp_double() { ret void } 45 46... 47--- 48name: test_trunc_s64 49# CHECK-LABEL: name: test_trunc_s64 50legalized: true 51regBankSelected: true 52selected: false 53# CHECK: selected: true 54registers: 55 - { id: 0, class: fprb } 56 - { id: 1, class: gprb } 57 - { id: 2, class: gprb } 58body: | 59 bb.0: 60 liveins: $r0, $d0 61 62 %0(s64) = COPY $d0 63 ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0 64 65 %2(p0) = COPY $r0 66 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 67 68 %1(s32) = G_TRUNC %0(s64) 69 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]] 70 71 G_STORE %1(s32), %2 :: (store 4) 72 ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14 /* CC::al */, $noreg 73 74 BX_RET 14, $noreg 75 ; CHECK: BX_RET 14 /* CC::al */, $noreg 76... 77--- 78name: test_fadd_s32 79# CHECK-LABEL: name: test_fadd_s32 80legalized: true 81regBankSelected: true 82selected: false 83# CHECK: selected: true 84registers: 85 - { id: 0, class: fprb } 86 - { id: 1, class: fprb } 87 - { id: 2, class: fprb } 88body: | 89 bb.0: 90 liveins: $s0, $s1 91 92 %0(s32) = COPY $s0 93 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 94 95 %1(s32) = COPY $s1 96 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 97 98 %2(s32) = G_FADD %0, %1 99 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 100 101 $s0 = COPY %2(s32) 102 ; CHECK: $s0 = COPY [[VREGSUM]] 103 104 BX_RET 14, $noreg, implicit $s0 105 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 106... 107--- 108name: test_fadd_s64 109# CHECK-LABEL: name: test_fadd_s64 110legalized: true 111regBankSelected: true 112selected: false 113# CHECK: selected: true 114registers: 115 - { id: 0, class: fprb } 116 - { id: 1, class: fprb } 117 - { id: 2, class: fprb } 118body: | 119 bb.0: 120 liveins: $d0, $d1 121 122 %0(s64) = COPY $d0 123 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 124 125 %1(s64) = COPY $d1 126 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 127 128 %2(s64) = G_FADD %0, %1 129 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 130 131 $d0 = COPY %2(s64) 132 ; CHECK: $d0 = COPY [[VREGSUM]] 133 134 BX_RET 14, $noreg, implicit $d0 135 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 136... 137--- 138name: test_fsub_s32 139# CHECK-LABEL: name: test_fsub_s32 140legalized: true 141regBankSelected: true 142selected: false 143# CHECK: selected: true 144registers: 145 - { id: 0, class: fprb } 146 - { id: 1, class: fprb } 147 - { id: 2, class: fprb } 148body: | 149 bb.0: 150 liveins: $s0, $s1 151 152 %0(s32) = COPY $s0 153 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 154 155 %1(s32) = COPY $s1 156 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 157 158 %2(s32) = G_FSUB %0, %1 159 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 160 161 $s0 = COPY %2(s32) 162 ; CHECK: $s0 = COPY [[VREGSUM]] 163 164 BX_RET 14, $noreg, implicit $s0 165 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 166... 167--- 168name: test_fsub_s64 169# CHECK-LABEL: name: test_fsub_s64 170legalized: true 171regBankSelected: true 172selected: false 173# CHECK: selected: true 174registers: 175 - { id: 0, class: fprb } 176 - { id: 1, class: fprb } 177 - { id: 2, class: fprb } 178body: | 179 bb.0: 180 liveins: $d0, $d1 181 182 %0(s64) = COPY $d0 183 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 184 185 %1(s64) = COPY $d1 186 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 187 188 %2(s64) = G_FSUB %0, %1 189 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 190 191 $d0 = COPY %2(s64) 192 ; CHECK: $d0 = COPY [[VREGSUM]] 193 194 BX_RET 14, $noreg, implicit $d0 195 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 196... 197--- 198name: test_fmul_s32 199# CHECK-LABEL: name: test_fmul_s32 200legalized: true 201regBankSelected: true 202selected: false 203# CHECK: selected: true 204registers: 205 - { id: 0, class: fprb } 206 - { id: 1, class: fprb } 207 - { id: 2, class: fprb } 208body: | 209 bb.0: 210 liveins: $s0, $s1 211 212 %0(s32) = COPY $s0 213 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 214 215 %1(s32) = COPY $s1 216 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 217 218 %2(s32) = G_FMUL %0, %1 219 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 220 221 $s0 = COPY %2(s32) 222 ; CHECK: $s0 = COPY [[VREGSUM]] 223 224 BX_RET 14, $noreg, implicit $s0 225 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 226... 227--- 228name: test_fmul_s64 229# CHECK-LABEL: name: test_fmul_s64 230legalized: true 231regBankSelected: true 232selected: false 233# CHECK: selected: true 234registers: 235 - { id: 0, class: fprb } 236 - { id: 1, class: fprb } 237 - { id: 2, class: fprb } 238body: | 239 bb.0: 240 liveins: $d0, $d1 241 242 %0(s64) = COPY $d0 243 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 244 245 %1(s64) = COPY $d1 246 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 247 248 %2(s64) = G_FMUL %0, %1 249 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 250 251 $d0 = COPY %2(s64) 252 ; CHECK: $d0 = COPY [[VREGSUM]] 253 254 BX_RET 14, $noreg, implicit $d0 255 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 256... 257--- 258name: test_fdiv_s32 259# CHECK-LABEL: name: test_fdiv_s32 260legalized: true 261regBankSelected: true 262selected: false 263# CHECK: selected: true 264registers: 265 - { id: 0, class: fprb } 266 - { id: 1, class: fprb } 267 - { id: 2, class: fprb } 268body: | 269 bb.0: 270 liveins: $s0, $s1 271 272 %0(s32) = COPY $s0 273 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 274 275 %1(s32) = COPY $s1 276 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 277 278 %2(s32) = G_FDIV %0, %1 279 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 280 281 $s0 = COPY %2(s32) 282 ; CHECK: $s0 = COPY [[VREGSUM]] 283 284 BX_RET 14, $noreg, implicit $s0 285 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 286... 287--- 288name: test_fdiv_s64 289# CHECK-LABEL: name: test_fdiv_s64 290legalized: true 291regBankSelected: true 292selected: false 293# CHECK: selected: true 294registers: 295 - { id: 0, class: fprb } 296 - { id: 1, class: fprb } 297 - { id: 2, class: fprb } 298body: | 299 bb.0: 300 liveins: $d0, $d1 301 302 %0(s64) = COPY $d0 303 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 304 305 %1(s64) = COPY $d1 306 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 307 308 %2(s64) = G_FDIV %0, %1 309 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 310 311 $d0 = COPY %2(s64) 312 ; CHECK: $d0 = COPY [[VREGSUM]] 313 314 BX_RET 14, $noreg, implicit $d0 315 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 316... 317--- 318name: test_fneg_s32 319# CHECK-LABEL: name: test_fneg_s32 320legalized: true 321regBankSelected: true 322selected: false 323# CHECK: selected: true 324registers: 325 - { id: 0, class: fprb } 326 - { id: 1, class: fprb } 327body: | 328 bb.0: 329 liveins: $s0 330 331 %0(s32) = COPY $s0 332 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 333 334 %1(s32) = G_FNEG %0 335 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14 /* CC::al */, $noreg 336 337 $s0 = COPY %1(s32) 338 ; CHECK: $s0 = COPY [[VREGSUM]] 339 340 BX_RET 14, $noreg, implicit $s0 341 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 342... 343--- 344name: test_fneg_s64 345# CHECK-LABEL: name: test_fneg_s64 346legalized: true 347regBankSelected: true 348selected: false 349# CHECK: selected: true 350registers: 351 - { id: 0, class: fprb } 352 - { id: 1, class: fprb } 353 - { id: 2, class: fprb } 354body: | 355 bb.0: 356 liveins: $d0 357 358 %0(s64) = COPY $d0 359 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 360 361 %1(s64) = G_FNEG %0 362 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14 /* CC::al */, $noreg 363 364 $d0 = COPY %1(s64) 365 ; CHECK: $d0 = COPY [[VREGSUM]] 366 367 BX_RET 14, $noreg, implicit $d0 368 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 369... 370--- 371name: test_fma_s32 372# CHECK-LABEL: name: test_fma_s32 373legalized: true 374regBankSelected: true 375selected: false 376# CHECK: selected: true 377registers: 378 - { id: 0, class: fprb } 379 - { id: 1, class: fprb } 380 - { id: 2, class: fprb } 381 - { id: 3, class: fprb } 382body: | 383 bb.0: 384 liveins: $s0, $s1, $s2 385 386 %0(s32) = COPY $s0 387 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 388 389 %1(s32) = COPY $s1 390 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 391 392 %2(s32) = COPY $s2 393 ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 394 395 %3(s32) = G_FMA %0, %1, %2 396 ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 397 398 $s0 = COPY %3(s32) 399 ; CHECK: $s0 = COPY [[VREGR]] 400 401 BX_RET 14, $noreg, implicit $s0 402 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 403... 404--- 405name: test_fma_s64 406# CHECK-LABEL: name: test_fma_s64 407legalized: true 408regBankSelected: true 409selected: false 410# CHECK: selected: true 411registers: 412 - { id: 0, class: fprb } 413 - { id: 1, class: fprb } 414 - { id: 2, class: fprb } 415 - { id: 3, class: fprb } 416body: | 417 bb.0: 418 liveins: $d0, $d1, $d2 419 420 %0(s64) = COPY $d0 421 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 422 423 %1(s64) = COPY $d1 424 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 425 426 %2(s64) = COPY $d2 427 ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 428 429 %3(s64) = G_FMA %0, %1, %2 430 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg 431 432 $d0 = COPY %3(s64) 433 ; CHECK: $d0 = COPY [[VREGR]] 434 435 BX_RET 14, $noreg, implicit $d0 436 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 437... 438--- 439name: test_fpext_s32_to_s64 440# CHECK-LABEL: name: test_fpext_s32_to_s64 441legalized: true 442regBankSelected: true 443selected: false 444# CHECK: selected: true 445registers: 446 - { id: 0, class: fprb } 447 - { id: 1, class: fprb } 448body: | 449 bb.0: 450 liveins: $s0 451 452 %0(s32) = COPY $s0 453 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 454 455 %1(s64) = G_FPEXT %0(s32) 456 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14 /* CC::al */, $noreg 457 458 $d0 = COPY %1(s64) 459 ; CHECK: $d0 = COPY [[VREGR]] 460 461 BX_RET 14, $noreg, implicit $d0 462 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 463... 464--- 465name: test_fptrunc_s64_to_s32 466# CHECK-LABEL: name: test_fptrunc_s64_to_s32 467legalized: true 468regBankSelected: true 469selected: false 470# CHECK: selected: true 471registers: 472 - { id: 0, class: fprb } 473 - { id: 1, class: fprb } 474body: | 475 bb.0: 476 liveins: $d0 477 478 %0(s64) = COPY $d0 479 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 480 481 %1(s32) = G_FPTRUNC %0(s64) 482 ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14 /* CC::al */, $noreg 483 484 $s0 = COPY %1(s32) 485 ; CHECK: $s0 = COPY [[VREGR]] 486 487 BX_RET 14, $noreg, implicit $s0 488 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 489... 490--- 491name: test_fptosi_s32 492# CHECK-LABEL: name: test_fptosi_s32 493legalized: true 494regBankSelected: true 495selected: false 496# CHECK: selected: true 497registers: 498 - { id: 0, class: fprb } 499 - { id: 1, class: gprb } 500body: | 501 bb.0: 502 liveins: $s0 503 504 %0(s32) = COPY $s0 505 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 506 507 %1(s32) = G_FPTOSI %0(s32) 508 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14 /* CC::al */, $noreg 509 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 510 511 $r0 = COPY %1(s32) 512 ; CHECK: $r0 = COPY [[VREGR]] 513 514 BX_RET 14, $noreg, implicit $r0 515 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 516... 517--- 518name: test_fptosi_s64 519# CHECK-LABEL: name: test_fptosi_s64 520legalized: true 521regBankSelected: true 522selected: false 523# CHECK: selected: true 524registers: 525 - { id: 0, class: fprb } 526 - { id: 1, class: gprb } 527body: | 528 bb.0: 529 liveins: $d0 530 531 %0(s64) = COPY $d0 532 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 533 534 %1(s32) = G_FPTOSI %0(s64) 535 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14 /* CC::al */, $noreg 536 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 537 538 $r0 = COPY %1(s32) 539 ; CHECK: $r0 = COPY [[VREGR]] 540 541 BX_RET 14, $noreg, implicit $r0 542 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 543... 544--- 545name: test_fptoui_s32 546# CHECK-LABEL: name: test_fptoui_s32 547legalized: true 548regBankSelected: true 549selected: false 550# CHECK: selected: true 551registers: 552 - { id: 0, class: fprb } 553 - { id: 1, class: gprb } 554body: | 555 bb.0: 556 liveins: $s0 557 558 %0(s32) = COPY $s0 559 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 560 561 %1(s32) = G_FPTOUI %0(s32) 562 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14 /* CC::al */, $noreg 563 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 564 565 $r0 = COPY %1(s32) 566 ; CHECK: $r0 = COPY [[VREGR]] 567 568 BX_RET 14, $noreg, implicit $r0 569 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 570... 571--- 572name: test_fptoui_s64 573# CHECK-LABEL: name: test_fptoui_s64 574legalized: true 575regBankSelected: true 576selected: false 577# CHECK: selected: true 578registers: 579 - { id: 0, class: fprb } 580 - { id: 1, class: gprb } 581body: | 582 bb.0: 583 liveins: $d0 584 585 %0(s64) = COPY $d0 586 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 587 588 %1(s32) = G_FPTOUI %0(s64) 589 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14 /* CC::al */, $noreg 590 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 591 592 $r0 = COPY %1(s32) 593 ; CHECK: $r0 = COPY [[VREGR]] 594 595 BX_RET 14, $noreg, implicit $r0 596 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 597... 598--- 599name: test_sitofp_s32 600# CHECK-LABEL: name: test_sitofp_s32 601legalized: true 602regBankSelected: true 603selected: false 604# CHECK: selected: true 605registers: 606 - { id: 0, class: gprb } 607 - { id: 1, class: fprb } 608body: | 609 bb.0: 610 liveins: $r0 611 612 %0(s32) = COPY $r0 613 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 614 615 %1(s32) = G_SITOFP %0(s32) 616 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 617 ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14 /* CC::al */, $noreg 618 619 $s0 = COPY %1(s32) 620 ; CHECK: $s0 = COPY [[VREGR]] 621 622 BX_RET 14, $noreg, implicit $s0 623 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 624... 625--- 626name: test_sitofp_s64 627# CHECK-LABEL: name: test_sitofp_s64 628legalized: true 629regBankSelected: true 630selected: false 631# CHECK: selected: true 632registers: 633 - { id: 0, class: gprb } 634 - { id: 1, class: fprb } 635body: | 636 bb.0: 637 liveins: $r0 638 639 %0(s32) = COPY $r0 640 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 641 642 %1(s64) = G_SITOFP %0(s32) 643 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 644 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14 /* CC::al */, $noreg 645 646 $d0 = COPY %1(s64) 647 ; CHECK: $d0 = COPY [[VREGR]] 648 649 BX_RET 14, $noreg, implicit $d0 650 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 651... 652--- 653name: test_uitofp_s32 654# CHECK-LABEL: name: test_uitofp_s32 655legalized: true 656regBankSelected: true 657selected: false 658# CHECK: selected: true 659registers: 660 - { id: 0, class: gprb } 661 - { id: 1, class: fprb } 662body: | 663 bb.0: 664 liveins: $r0 665 666 %0(s32) = COPY $r0 667 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 668 669 %1(s32) = G_UITOFP %0(s32) 670 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 671 ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14 /* CC::al */, $noreg 672 673 $s0 = COPY %1(s32) 674 ; CHECK: $s0 = COPY [[VREGR]] 675 676 BX_RET 14, $noreg, implicit $s0 677 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 678... 679--- 680name: test_uitofp_s64 681# CHECK-LABEL: name: test_uitofp_s64 682legalized: true 683regBankSelected: true 684selected: false 685# CHECK: selected: true 686registers: 687 - { id: 0, class: gprb } 688 - { id: 1, class: fprb } 689body: | 690 bb.0: 691 liveins: $r0 692 693 %0(s32) = COPY $r0 694 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 695 696 %1(s64) = G_UITOFP %0(s32) 697 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 698 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14 /* CC::al */, $noreg 699 700 $d0 = COPY %1(s64) 701 ; CHECK: $d0 = COPY [[VREGR]] 702 703 BX_RET 14, $noreg, implicit $d0 704 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 705... 706--- 707name: test_load_f32 708# CHECK-LABEL: name: test_load_f32 709legalized: true 710regBankSelected: true 711selected: false 712# CHECK: selected: true 713registers: 714 - { id: 0, class: gprb } 715 - { id: 1, class: fprb } 716body: | 717 bb.0: 718 liveins: $r0 719 720 %0(p0) = COPY $r0 721 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 722 723 %1(s32) = G_LOAD %0(p0) :: (load 4) 724 ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14 /* CC::al */, $noreg 725 726 $s0 = COPY %1 727 ; CHECK: $s0 = COPY %[[V]] 728 729 BX_RET 14, $noreg, implicit $s0 730 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 731... 732--- 733name: test_load_f64 734# CHECK-LABEL: name: test_load_f64 735legalized: true 736regBankSelected: true 737selected: false 738# CHECK: selected: true 739registers: 740 - { id: 0, class: gprb } 741 - { id: 1, class: fprb } 742body: | 743 bb.0: 744 liveins: $r0 745 746 %0(p0) = COPY $r0 747 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 748 749 %1(s64) = G_LOAD %0(p0) :: (load 8) 750 ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14 /* CC::al */, $noreg 751 752 $d0 = COPY %1 753 ; CHECK: $d0 = COPY %[[V]] 754 755 BX_RET 14, $noreg, implicit $d0 756 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 757... 758--- 759name: test_stores 760# CHECK-LABEL: name: test_stores 761legalized: true 762regBankSelected: true 763selected: false 764# CHECK: selected: true 765registers: 766 - { id: 0, class: gprb } 767 - { id: 1, class: fprb } 768 - { id: 2, class: fprb } 769# CHECK: id: [[P:[0-9]+]], class: gpr 770# CHECK: id: [[F32:[0-9]+]], class: spr 771# CHECK: id: [[F64:[0-9]+]], class: dpr 772body: | 773 bb.0: 774 liveins: $r0, $s0, $d0 775 776 %0(p0) = COPY $r0 777 %1(s32) = COPY $s0 778 %2(s64) = COPY $d2 779 780 G_STORE %1(s32), %0(p0) :: (store 4) 781 ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14 /* CC::al */, $noreg 782 783 G_STORE %2(s64), %0(p0) :: (store 8) 784 ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14 /* CC::al */, $noreg 785 786 BX_RET 14, $noreg 787... 788--- 789name: test_phi_s64 790# CHECK-LABEL: name: test_phi_s64 791legalized: true 792regBankSelected: true 793selected: false 794# CHECK: selected: true 795tracksRegLiveness: true 796registers: 797 - { id: 0, class: gprb } 798 - { id: 1, class: gprb } 799 - { id: 2, class: fprb } 800 - { id: 3, class: fprb } 801 - { id: 4, class: fprb } 802body: | 803 bb.0: 804 ; CHECK: [[BB1:bb.0]]: 805 successors: %bb.1(0x40000000), %bb.2(0x40000000) 806 liveins: $r0, $d0, $d1 807 808 %0(s32) = COPY $r0 809 %1(s1) = G_TRUNC %0(s32) 810 811 %2(s64) = COPY $d0 812 %3(s64) = COPY $d1 813 ; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0 814 ; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1 815 816 G_BRCOND %1(s1), %bb.1 817 G_BR %bb.2 818 819 bb.1: 820 ; CHECK: [[BB2:bb.1]]: 821 successors: %bb.2(0x80000000) 822 823 G_BR %bb.2 824 ; CHECK: B %bb.2 825 826 bb.2: 827 ; CHECK: bb.2 828 %4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1 829 ; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] 830 831 $d0 = COPY %4(s64) 832 BX_RET 14 /* CC::al */, $noreg, implicit $d0 833... 834--- 835name: test_soft_fp_double 836# CHECK-LABEL: name: test_soft_fp_double 837legalized: true 838regBankSelected: true 839selected: false 840# CHECK: selected: true 841registers: 842 - { id: 0, class: gprb } 843 - { id: 1, class: gprb } 844 - { id: 2, class: fprb } 845 - { id: 3, class: gprb } 846 - { id: 4, class: gprb } 847body: | 848 bb.0: 849 liveins: $r0, $r1, $r2, $r3 850 851 %0(s32) = COPY $r2 852 ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2 853 854 %1(s32) = COPY $r3 855 ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3 856 857 %2(s64) = G_MERGE_VALUES %0(s32), %1(s32) 858 ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]] 859 860 %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) 861 ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]] 862 863 $r0 = COPY %3 864 ; CHECK: $r0 = COPY [[OUT1]] 865 866 $r1 = COPY %4 867 ; CHECK: $r1 = COPY [[OUT2]] 868 869 BX_RET 14, $noreg, implicit $r0, implicit $r1 870 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 871... 872