| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 55 VOPC = 1 << 10 variable in Format
836 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
842 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
844 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
846 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
848 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
852 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
854 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
856 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
858 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
[all …]
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| D | aco_validate.cpp | 116 else if ((uint32_t)base_format & (uint32_t)Format::VOPC) in validate_ir()
117 base_format = Format::VOPC; in validate_ir()
137 base_format == Format::VOPC || in validate_ir()
146 base_format == Format::VOPC, in validate_ir()
153 if (base_format == Format::VOPC) { in validate_ir()
242 instr->format == Format::VOPC || in validate_ir()
264 if ((int) instr->format & (int) Format::VOPC || in validate_ir()
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| D | aco_ir.cpp | 174 if (vop3->clamp && instr->format == asVOP3(Format::VOPC) && chip != GFX8) in can_use_SDWA()
207 if ((unsigned)instr->format & (unsigned)Format::VOPC) in can_use_SDWA()
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| D | aco_ir.h | 101 VOPC = 1 << 10, enumerator
242 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
920 || ((uint16_t) format & (uint16_t) Format::VOPC) == (uint16_t) Format::VOPC in isVALU()
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| D | aco_optimizer.cpp | 1093 if ((uint16_t) instr->format & (uint16_t) Format::VOPC) { in label_instruction()
1371 if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */ in label_instruction()
1695 …VOP3A_instruction *vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1… in combine_ordering_test()
1703 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_ordering_test()
1766 …_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_comparison_ordering()
1775 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_comparison_ordering()
1885 …_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_constant_comparison_ordering()
1894 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_constant_comparison_ordering()
1934 …truction *new_vop3 = create_instruction<VOP3A_instruction>(new_opcode, asVOP3(Format::VOPC), 2, 1); in combine_inverse_comparison()
1944 new_opcode, (Format)((uint16_t)Format::SDWA | (uint16_t)Format::VOPC), 2, 1); in combine_inverse_comparison()
[all …]
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| D | aco_assembler.cpp | 278 case Format::VOPC: { in emit_instruction()
559 } else if ((uint16_t) instr->format & (uint16_t) Format::VOPC) { in emit_instruction()
659 if ((uint16_t)instr->format & (uint16_t)Format::VOPC) { in emit_instruction()
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| D | aco_insert_NOPs.cpp | 543 if ((uint32_t) instr->format & (uint32_t) Format::VOPC) in VALU_writes_sgpr()
636 if (instr->format == Format::VOPC) { in handle_instruction_gfx10()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstrFormats.td | 146 // Encoding used for VOPC instructions encoded as VOP3
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
286 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
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| D | SIInstrFormats.td | 34 field bits<1> VOPC = 0;
70 let TSFlags{13} = VOPC;
127 let VOPC = 1;
429 // Encoding used for VOPC instructions encoded as VOP3
430 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
653 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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| D | SIDefines.h | 31 VOPC = 1 << 13, enumerator
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| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrInfo.h | 272 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
276 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUInstructionSyntax.rst | 125 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
134 Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 30 field bit VOPC = 0;
150 let TSFlags{9} = VOPC;
213 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| D | VOPCInstructions.td | 31 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
48 // VOPC classes
51 // VOPC instructions are a special case because for the 32-bit
98 let VOPC = 1;
131 // This class is used only with VOPC instructions. Use $sdst for out operand
888 // Encoding used for VOPC instructions encoded as VOP3 differs from
889 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1005 // Encoding used for VOPC instructions encoded as VOP3 differs from
1006 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1235 // Encoding used for VOPC instructions encoded as VOP3
[all …]
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| D | SIInstrInfo.td | 1448 SDWAVopcDst, // VOPC
1857 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1875 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1889 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1954 ""); // use $sdst for VOPC
1974 ""); // use $sdst for VOPC
1988 " vcc", // use vcc token as dst for VOPC instructioins
2005 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2017 "$sdst", // VOPC
2033 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
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| D | SISchedule.td | 63 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIDefines.h | 34 VOPC = 1 << 9, enumerator
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 30 field bit VOPC = 0;
142 let TSFlags{9} = VOPC;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
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| D | VOPCInstructions.td | 31 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
48 // VOPC classes
51 // VOPC instructions are a special case because for the 32-bit
96 let VOPC = 1;
129 // This class is used only with VOPC instructions. Use $sdst for out operand
882 // Encoding used for VOPC instructions encoded as VOP3 differs from
883 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
999 // Encoding used for VOPC instructions encoded as VOP3 differs from
1000 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1229 // Encoding used for VOPC instructions encoded as VOP3
[all …]
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| D | SIInstrInfo.td | 1458 SDWAVopcDst, // VOPC
1865 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1883 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1897 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1962 ""); // use $sdst for VOPC
1982 ""); // use $sdst for VOPC
1996 " vcc", // use vcc token as dst for VOPC instructioins
2013 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
2025 "$sdst", // VOPC
2041 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
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| D | SIDefines.h | 34 VOPC = 1 << 9, enumerator
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| D | SISchedule.td | 55 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrInfo.h | 438 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
442 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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