1//===-- SISchedule.td - SI Scheduling definitons -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// MachineModel definitions for Southern Islands (SI) 11// 12//===----------------------------------------------------------------------===// 13 14def : PredicateProlog<[{ 15 const SIInstrInfo *TII = 16 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo()); 17 (void)TII; 18}]>; 19 20def WriteBranch : SchedWrite; 21def WriteExport : SchedWrite; 22def WriteLDS : SchedWrite; 23def WriteSALU : SchedWrite; 24def WriteSMEM : SchedWrite; 25def WriteVMEM : SchedWrite; 26def WriteBarrier : SchedWrite; 27 28// Vector ALU instructions 29def Write32Bit : SchedWrite; 30def WriteQuarterRate32 : SchedWrite; 31def WriteFullOrQuarterRate32 : SchedWrite; 32 33def WriteFloatFMA : SchedWrite; 34 35// Slow quarter rate f64 instruction. 36def WriteDouble : SchedWrite; 37 38// half rate f64 instruction (same as v_add_f64) 39def WriteDoubleAdd : SchedWrite; 40 41// Half rate 64-bit instructions. 42def Write64Bit : SchedWrite; 43 44// FIXME: Should there be a class for instructions which are VALU 45// instructions and have VALU rates, but write to the SALU (i.e. VOPC 46// instructions) 47 48class SISchedMachineModel : SchedMachineModel { 49 let CompleteModel = 0; 50 let IssueWidth = 1; 51 let PostRAScheduler = 1; 52} 53 54def SIFullSpeedModel : SISchedMachineModel; 55def SIQuarterSpeedModel : SISchedMachineModel; 56 57// XXX: Are the resource counts correct? 58def HWBranch : ProcResource<1> { 59 let BufferSize = 1; 60} 61def HWExport : ProcResource<1> { 62 let BufferSize = 7; // Taken from S_WAITCNT 63} 64def HWLGKM : ProcResource<1> { 65 let BufferSize = 31; // Taken from S_WAITCNT 66} 67def HWSALU : ProcResource<1> { 68 let BufferSize = 1; 69} 70def HWVMEM : ProcResource<1> { 71 let BufferSize = 15; // Taken from S_WAITCNT 72} 73def HWVALU : ProcResource<1> { 74 let BufferSize = 1; 75} 76 77class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources, 78 int latency> : WriteRes<write, resources> { 79 let Latency = latency; 80} 81 82class HWVALUWriteRes<SchedWrite write, int latency> : 83 HWWriteRes<write, [HWVALU], latency>; 84 85 86// The latency numbers are taken from AMD Accelerated Parallel Processing 87// guide. They may not be accurate. 88 89// The latency values are 1 / (operations / cycle) / 4. 90multiclass SICommonWriteRes { 91 92 def : HWWriteRes<WriteBranch, [HWBranch], 8>; 93 def : HWWriteRes<WriteExport, [HWExport], 4>; 94 def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64 95 def : HWWriteRes<WriteSALU, [HWSALU], 1>; 96 def : HWWriteRes<WriteSMEM, [HWLGKM], 5>; 97 def : HWWriteRes<WriteVMEM, [HWVMEM], 80>; 98 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ??? 99 100 def : HWVALUWriteRes<Write32Bit, 1>; 101 def : HWVALUWriteRes<Write64Bit, 2>; 102 def : HWVALUWriteRes<WriteQuarterRate32, 4>; 103} 104 105def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>; 106def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>; 107def WriteCopy : SchedWriteVariant<[ 108 SchedVar<PredIsVGPR32Copy, [Write32Bit]>, 109 SchedVar<PredIsVGPR64Copy, [Write64Bit]>, 110 SchedVar<NoSchedPred, [WriteSALU]>]>; 111 112let SchedModel = SIFullSpeedModel in { 113 114defm : SICommonWriteRes; 115 116def : HWVALUWriteRes<WriteFloatFMA, 1>; 117def : HWVALUWriteRes<WriteDouble, 4>; 118def : HWVALUWriteRes<WriteDoubleAdd, 2>; 119 120def : InstRW<[WriteCopy], (instrs COPY)>; 121 122} // End SchedModel = SIFullSpeedModel 123 124let SchedModel = SIQuarterSpeedModel in { 125 126defm : SICommonWriteRes; 127 128def : HWVALUWriteRes<WriteFloatFMA, 16>; 129def : HWVALUWriteRes<WriteDouble, 16>; 130def : HWVALUWriteRes<WriteDoubleAdd, 8>; 131 132def : InstRW<[WriteCopy], (instrs COPY)>; 133 134} // End SchedModel = SIQuarterSpeedModel 135