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Searched refs:VPR (Results 1 – 25 of 36) sorted by relevance

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/external/llvm-project/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp75 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
77 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
129 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR)) in IsVPRDefinedOrKilledByBlock()
DMVEVPTOptimisationsPass.cpp666 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local
667 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs()
671 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs()
695 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs()
697 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
714 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
721 VPR = NewVPR; in ReplaceConstByVPNOTs()
725 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
DARMLowOverheadLoops.cpp84 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
88 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
92 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1; in hasVPRUse()
194 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock()
993 if (RegMask.PhysReg == ARM::VPR) in ValidateLiveOuts()
1147 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
1526 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
DARMRegisterInfo.td201 // on the instruction they are used in and for VPR 32 was chosen such that it
203 def VPR : ARMReg<32, "vpr">;
369 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
427 // Scalar single and double precision floating point and VPR register class,
430 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
DARMInstrVFP.td326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
2484 // System level VPR/P0 -> GPR
2485 let Uses = [VPR] in
2555 // System level GPR -> VPR/P0
2556 let Defs = [VPR] in
2844 let Uses = [VPR] in {
2850 let Defs = [VPR] in {
DARMExpandPseudoInsts.cpp1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1211 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1289 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1383 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
DARMBaseInstrInfo.cpp832 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
940 } else if (DestReg == ARM::VPR) { in copyPhysReg()
946 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp78 auto *Def = RDA->getReachingMIDef(MI, ARM::VPR); in findVCMPToFoldIntoVPST()
DARMRegisterInfo.td201 // on the instruction they are used in and for VPR 32 was chosen such that it
203 def VPR : ARMReg<32, "vpr">;
358 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
416 // Scalar single and double precision floating point and VPR register class,
419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
DARMLowOverheadLoops.cpp516 if (!MO.isReg() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
DARMInstrVFP.td2388 // System level VPR/P0 -> GPR
2389 let Uses = [VPR] in
2459 // System level GPR -> VPR/P0
2460 let Defs = [VPR] in
2743 let Uses = [VPR] in {
2761 let Defs = [VPR] in {
DARMBaseInstrInfo.cpp821 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
929 } else if (DestReg == ARM::VPR) { in copyPhysReg()
935 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
DARMInstrMVE.td3918 // example when moving between rGPR and VPR.P0 as part of predicate vector
5512 let Defs = [VPR];
5623 let Defs = [VPR];
5669 let Uses = [VPR];
/external/llvm/test/CodeGen/AArch64/
Darm64-aapcs.ll117 ; Check if VPR can be correctly pass by stack.
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-aapcs.ll116 ; Check if VPR can be correctly pass by stack.
/external/llvm/include/llvm/ProfileData/
DInstrProfData.inc399 getValueProfRecordNext(ValueProfRecord *VPR);
401 getValueProfRecordValueData(ValueProfRecord *VPR);
/external/compiler-rt/lib/profile/
DInstrProfData.inc399 getValueProfRecordNext(ValueProfRecord *VPR);
401 getValueProfRecordValueData(ValueProfRecord *VPR);
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ProfileData/
DInstrProfData.inc440 getValueProfRecordNext(ValueProfRecord *VPR);
442 getValueProfRecordValueData(ValueProfRecord *VPR);
/external/llvm-project/compiler-rt/include/profile/
DInstrProfData.inc455 getValueProfRecordNext(ValueProfRecord *VPR);
457 getValueProfRecordValueData(ValueProfRecord *VPR);
/external/llvm-project/llvm/include/llvm/ProfileData/
DInstrProfData.inc455 getValueProfRecordNext(ValueProfRecord *VPR);
457 getValueProfRecordValueData(ValueProfRecord *VPR);
/external/llvm-project/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5921 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5942 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6132 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6599 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6636 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6646 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6647 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5898 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5919 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6092 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6569 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6606 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6616 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6617 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-vpt-optimisations.mir617 ; VCCR/VPR is written to in-between.
936 ; that writes to VPR, and that doesn't use any of the registers we care about.
/external/llvm/lib/Transforms/Vectorize/
DBBVectorize.cpp2085 ValuePair VPR = ValuePair(O2, O1); in findBestDAGFor() local
2088 if (PrunedDAG.count(VP) || PrunedDAG.count(VPR)) in findBestDAGFor()
2133 } else if (IncomingPairs.count(VPR)) { in findBestDAGFor()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3541 if (Regs.back().second == ARM::VPR) in CreateRegList()
3547 if (Regs.back().second == ARM::VPR) in CreateRegList()
4381 if (Reg == ARM::VPR && in parseRegisterList()

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