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Searched refs:VREG (Results 1 – 25 of 37) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/X86/
Dstatepoint-vreg-details.ll6 …x-registers-for-gc-values=4 -stop-after finalize-isel < %s | FileCheck --check-prefix=CHECK-VREG %s
25 ; CHECK-VREG-LABEL: name: test_relocate
26 ; CHECK-VREG: %0:gr64 = COPY $rdi
27 ; CHECK-VREG: %1:gr64 = STATEPOINT 0, 0, 0, @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, %0(tied-def 0), …
28 ; CHECK-VREG: %2:gr8 = COPY $al
29 ; CHECK-VREG: $rdi = COPY %1
30 ; CHECK-VREG: CALL64pcrel32 @consume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, impli…
48 ; CHECK-VREG-LABEL: name: test_mixed
49 ; CHECK-VREG: %2:gr64 = COPY $rdx
50 ; CHECK-VREG: %1:gr64 = COPY $rsi
[all …]
Dstatepoint-vreg-unlimited-tied-opnds.ll1 …c -max-registers-for-gc-values=18 -stop-before greedy < %s | FileCheck --check-prefix=CHECK-VREG %s
14 ; CHECK-VREG-LABEL: test_spill
15 ; CHECK-VREG: %18:gr64 = COPY $r9
16 ; CHECK-VREG: %19:gr64 = COPY $r8
17 ; CHECK-VREG: %20:gr64 = COPY $rcx
18 ; CHECK-VREG: %21:gr64 = COPY $rdx
19 ; CHECK-VREG: %22:gr64 = COPY $rsi
20 ; CHECK-VREG: %23:gr64 = COPY $rdi
21 ; CHECK-VREG: %17:gr64 = MOV64rm %fixed-stack.11, 1, $noreg, 0, $noreg :: (load 8 from %fixed-s…
22 ; CHECK-VREG: %16:gr64 = MOV64rm %fixed-stack.10, 1, $noreg, 0, $noreg :: (load 8 from %fixed-s…
[all …]
Dtail-dup-debugloc.ll7 ; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY $rdi
8 ; CHECK: TEST64rr [[VREG]], [[VREG]]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.bfe.i32.ll88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
89 ; SI: buffer_store_dword [[VREG]],
183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
184 ; SI: buffer_store_dword [[VREG]],
195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
208 ; SI: buffer_store_dword [[VREG]],
219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
220 ; SI: buffer_store_dword [[VREG]],
[all …]
Dllvm.AMDGPU.bfe.u32.ll195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
331 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
332 ; SI: buffer_store_dword [[VREG]],
343 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
344 ; SI: buffer_store_dword [[VREG]],
355 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
356 ; SI: buffer_store_dword [[VREG]],
367 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
368 ; SI: buffer_store_dword [[VREG]],
[all …]
Dtrunc-store-i1.ll8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; SI: buffer_store_byte [[VREG]],
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
28 ; SI: buffer_store_byte [[VREG]],
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.sbfe.ll78 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
79 ; GCN: buffer_store_dword [[VREG]],
173 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
174 ; GCN: buffer_store_dword [[VREG]],
184 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
185 ; GCN: buffer_store_dword [[VREG]],
195 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; GCN: buffer_store_dword [[VREG]],
206 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
207 ; GCN: buffer_store_dword [[VREG]],
[all …]
Dtrunc-store-i1.ll8 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; GCN: buffer_store_byte [[VREG]],
28 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
29 ; GCN: buffer_store_byte [[VREG]],
Dfexp.ll125 ; VI-NEXT: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
126 ; VI-NEXT: v_mul_f16_sdwa [[MUL1:v[0-9]+]], v{{[0-9]+}}, [[VREG]] dst_sel:DWORD dst_unused:UNUSE…
179 ; VI-NEXT: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
182 ; VI-NEXT: v_mul_f16_sdwa [[MUL3:v[0-9]+]], v1, [[VREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
183 ; VI-NEXT: v_mul_f16_sdwa [[MUL4:v[0-9]+]], v0, [[VREG]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
Dtrunc.ll59 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
69 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
Dmai-inline.ll5 ; GFX908: v_accvgpr_read [[VREG:v[0-9]+]], [[AREG]]
6 ; GFX908: global_store_dword v{{[0-9]+}}, [[VREG]], s{{\[[0-9]+:[0-9]+\]}}
/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/
Dselect-fp-const.mir35 …; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constan…
38 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
66 …; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constan…
69 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
98 ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
99 …; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load 4 from constant…
102 ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
131 ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg
132 …; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load 8 from constant…
135 ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dmemcpy_dereferenceable.ll6 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
8 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
9 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
39 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
41 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
42 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
Dppc32-pic.ll27 ; SMALL-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
28 ; SMALL-DAG: lwz {{[0-9]+}}, 0([[VREG]])
Dppc32-pic-large.ll44 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
45 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSDNodeDbgValue.h36 VREG = 3 ///< Value is a virtual register. enumerator
80 assert((Kind == VREG || Kind == FRAMEIX) && in SDDbgValue()
83 if (kind == VREG) in SDDbgValue()
111 unsigned getVReg() const { assert (kind==VREG); return u.VReg; } in getVReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSDNodeDbgValue.h36 VREG = 3 ///< Value is a virtual register. enumerator
80 assert((Kind == VREG || Kind == FRAMEIX) && in SDDbgValue()
83 if (kind == VREG) in SDDbgValue()
111 unsigned getVReg() const { assert (kind==VREG); return u.VReg; } in getVReg()
/external/llvm/test/CodeGen/PowerPC/
Dppc32-pic.ll21 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
22 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
Dppc32-pic-large.ll24 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
25 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/external/llvm/test/CodeGen/SystemZ/
Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/X86/
Dremove-debug-2.ll15 ; CHECK: [[VREG:%[^ ]+]] = select
16 ; CHECK: store i32 [[VREG]],{{.*}} !dbg [[storeLoc:![0-9]+]]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-prolog-phi.ll8 ; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
9 ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
/external/pdfium/third_party/libopenjpeg20/
Ddwt.c602 #define VREG __m256i macro
604 #define LOAD(x) _mm256_load_si256((const VREG*)(x))
605 #define LOADU(x) _mm256_loadu_si256((const VREG*)(x))
606 #define STORE(x,y) _mm256_store_si256((VREG*)(x),(y))
607 #define STOREU(x,y) _mm256_storeu_si256((VREG*)(x),(y))
612 #define VREG __m128i macro
614 #define LOAD(x) _mm_load_si128((const VREG*)(x))
615 #define LOADU(x) _mm_loadu_si128((const VREG*)(x))
616 #define STORE(x,y) _mm_store_si128((VREG*)(x),(y))
617 #define STOREU(x,y) _mm_storeu_si128((VREG*)(x),(y))
[all …]
/external/llvm-project/llvm/test/DebugInfo/MIR/X86/
Dsink-leaves-undef.mir95 ; CHECK: %[[VREG:[0-9]+]]:gr32 = MOV32rm
96 ; CHECK-NEXT: DBG_VALUE %[[VREG]], $noreg, ![[VARNUM]]

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