| /external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1050 @ cost of extra REV and VREV32 operations in little-endian ARM.
1152 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1023 @ cost of extra REV and VREV32 operations in little-endian ARM.
1123 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1023 @ cost of extra REV and VREV32 operations in little-endian ARM.
1123 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/ |
| D | vpaes-armv7.S | 1023 @ cost of extra REV and VREV32 operations in little-endian ARM.
1123 @ cost of extra REV and VREV32 operations in little-endian ARM.
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 2975 VREV32 output:
2976 VREV32:22:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
2977 VREV32:23:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
2978 VREV32:24:result_int32x2 [] = { 33333333, 33333333, }
2979 VREV32:25:result_int64x1 [] = { 3333333333333333, }
2980 VREV32:26:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
2981 VREV32:27:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
2982 VREV32:28:result_uint32x2 [] = { 33333333, 33333333, }
2983 VREV32:29:result_uint64x1 [] = { 3333333333333333, }
2984 VREV32:30:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
|
| D | ref-rvct-neon.txt | 3397 VREV32 output:
3398 VREV32:24:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
3399 VREV32:25:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
3400 VREV32:26:result_int32x2 [] = { 33333333, 33333333, }
3401 VREV32:27:result_int64x1 [] = { 3333333333333333, }
3402 VREV32:28:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
3403 VREV32:29:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
3404 VREV32:30:result_uint32x2 [] = { 33333333, 33333333, }
3405 VREV32:31:result_uint64x1 [] = { 3333333333333333, }
3406 VREV32:32:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
|
| D | ref-rvct-all.txt | 3397 VREV32 output:
3398 VREV32:24:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
3399 VREV32:25:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
3400 VREV32:26:result_int32x2 [] = { 33333333, 33333333, }
3401 VREV32:27:result_int64x1 [] = { 3333333333333333, }
3402 VREV32:28:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
3403 VREV32:29:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
3404 VREV32:30:result_uint32x2 [] = { 33333333, 33333333, }
3405 VREV32:31:result_uint64x1 [] = { 3333333333333333, }
3406 VREV32:32:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 154 VREV32, // reverse elements within 32-bit words enumerator
|
| D | ARMScheduleSwift.td | 549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1209 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
4767 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements()
6146 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
6271 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| D | ARMInstrNEON.td | 575 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
6287 // VREV32 : Vector Reverse elements within 32-bit words
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 195 VREV32, // reverse elements within 32-bit words enumerator
|
| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1645 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
7697 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
8000 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 198 VREV32, // reverse elements within 32-bit words enumerator
|
| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1711 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
8003 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
8306 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
9554 unsigned RevOpcode = NumActiveLanes == 16 ? ARMISD::VREV16 : ARMISD::VREV32; in LowerVecReduce()
|
| D | ARMInstrInfo.td | 261 def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 254 VREV32.16 D4,D27
|
| D | ihevc_resi_trans.s | 1131 VREV32.16 D2,D27 @1-cycle stall before it?
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 784 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 640 def VREV32 : WOpInst<"vrev32", "..", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 449 // FastEmit functions for ARMISD::VREV32.
2752 case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill);
|