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Searched refs:VREV64 (Results 1 – 25 of 35) sorted by relevance

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/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s52 VREV64.32 Q1, Q1
89 VREV64.32 Q2, Q2
92 VREV64.32 Q3, Q3
100 VREV64.16 D10, D10
121 VREV64.32 Q2, Q2
126 VREV64.32 Q3, Q3
137 VREV64.32 Q7, Q7
138 VREV64.32 Q6, Q6
141 VREV64.16 D10, D10
165 VREV64.32 Q2, Q2
[all …]
Dixheaacd_overlap_add2.s56 VREV64.16 D4, D6
57 VREV64.16 D5, D7
71 VREV64.16 Q6, Q7
85 VREV64.16 D4, D6
87 VREV64.16 D5, D7
106 VREV64.16 Q6, Q7
160 VREV64.32 D0, D6
161 VREV64.32 D1, D7
166 VREV64.16 D2, D2
167 VREV64.16 D3, D3
[all …]
Dixheaacd_dct3_32.s58 VREV64.32 Q1, Q1
75 VREV64.32 Q4, Q4
90 VREV64.32 Q1, Q1
120 VREV64.32 Q4, Q4
137 VREV64.32 Q1, Q1
153 VREV64.32 Q4, Q4
292 VREV64.32 Q2, Q2
295 VREV64.32 Q3, Q3
308 VREV64.16 D8, D8
344 VREV64.32 Q13, Q13
[all …]
Dixheaacd_pre_twiddle_compute.s111 VREV64.16 Q5, Q4
116 VREV64.16 Q0, Q0
117 VREV64.16 Q2, Q2
168 VREV64.16 Q5, Q4
178 VREV64.16 Q0, Q0
181 VREV64.16 Q2, Q2
237 VREV64.16 Q5, Q4
244 VREV64.16 Q0, Q0
247 VREV64.16 Q2, Q2
326 VREV64.16 Q0, Q0
[all …]
Dixheaacd_no_lap1.s48 VREV64.32 Q13, Q13
67 VREV64.32 Q10, Q10
79 VREV64.32 Q13, Q13
99 VREV64.32 Q10, Q10
Dixheaacd_post_twiddle.s110 VREV64.16 Q6, Q4
168 VREV64.16 Q6, Q4
191 VREV64.32 Q7, Q7
204 VREV64.32 Q12, Q12
276 VREV64.16 Q6, Q4
299 VREV64.32 Q7, Q7
310 VREV64.32 Q12, Q12
399 VREV64.32 Q7, Q7
410 VREV64.32 Q12, Q12
435 VREV64.16 Q6, Q4
[all …]
Dixheaacd_overlap_add1.s49 VREV64.32 Q3, Q3
60 VREV64.16 Q1, Q1
106 VREV64.32 Q3, Q3
115 VREV64.16 Q1, Q1
149 VREV64.32 Q3, Q3
168 VREV64.16 Q1, Q1
212 VREV64.32 Q3, Q3
220 VREV64.16 Q1, Q1
Dixheaacd_mps_synt_post_fft_twiddle.s56 VREV64.32 D1, D1
57 VREV64.32 D0, D0
Dixheaacd_calc_pre_twid.s44 VREV64.32 D8, D8
45 VREV64.32 D9, D10
Dixheaacd_post_twiddle_overlap.s195 VREV64.16 Q0, Q0
196 VREV64.16 Q1, Q1
220 VREV64.16 Q5, Q5
223 VREV64.16 Q6, Q6
391 VREV64.16 Q0, Q0
394 VREV64.16 Q1, Q1
408 VREV64.16 Q5, Q5
411 VREV64.16 Q6, Q6
654 VREV64.16 Q0, Q0
657 VREV64.16 Q1, Q1
[all …]
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s201 VREV64.S16 Q10,Q10 @ Rev 17-24 row 1 -- dual issue
203 VREV64.S16 Q11,Q11 @ Rev 25-32 row 1 -- dual issue
209 VREV64.S16 Q2,Q2 @ Rev 17-24 row 2
211 VREV64.S16 Q3,Q3 @ Rev 25-32 row 2
218 VREV64.16 Q5, Q5 @ Rev 9-16 of e[k], row 1
223 VREV64.16 Q9, Q9 @ Rev 9-16 of e[k], row 2
230 VREV64.S16 D8,D1 @ rev ee[k] k-> 4-7 row 1
234 VREV64.S16 D9,D5 @ rev ee[k] k-> 4-7 row 2
837 VREV64.32 Q15,Q15 @ Q15: [16 1] [16 0] [24 1] [24 0]
854 VREV64.S32 Q4,Q4 @Rev 17-20 R1
[all …]
Dihevc_resi_trans.s1105 VREV64.S16 Q5,Q5 @Rev row 1
1106 VREV64.S16 Q7,Q7 @Rev row 2
1115 VREV64.S16 D24,D17 @rev e[k] k-> 4-7 row 1
1116 VREV64.S16 D25,D21 @rev e[k] k-> 4-7 row 2
1429 VREV64.32 Q15,Q15
1450 VREV64.S32 Q2,Q2 @Rev 9-12 R1
1451 VREV64.S32 Q3,Q3 @Rev 12-16 R1
1452 VREV64.S32 Q6,Q6 @Rev 9-12 R2
1453 VREV64.S32 Q7,Q7 @Rev 12-16 R2
1465 VREV64.S32 Q9 ,Q9 @rev e[k] k-> 4-7 R1, dual issued with prev. instruction
[all …]
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt2999 VREV64 output:
3000 VREV64:44:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3001 VREV64:45:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3002 VREV64:46:result_int32x2 [] = { fffffff1, fffffff0, }
3003 VREV64:47:result_int64x1 [] = { 3333333333333333, }
3004 VREV64:48:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3005 VREV64:49:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3006 VREV64:50:result_uint32x2 [] = { fffffff1, fffffff0, }
3007 VREV64:51:result_uint64x1 [] = { 3333333333333333, }
3008 VREV64:52:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
Dref-rvct-neon.txt3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
Dref-rvct-all.txt3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.h153 VREV64, // reverse elements within 64-bit doublewords enumerator
DARMScheduleSwift.td549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
DARMISelLowering.cpp1208 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6143 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6206 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6269 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.h194 VREV64, // reverse elements within 64-bit doublewords enumerator
DARMScheduleSwift.td565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
DARMISelLowering.cpp1644 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
5817 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6253 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
7694 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
7757 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
7998 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.h197 VREV64, // reverse elements within 64-bit doublewords enumerator
DARMScheduleSwift.td565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
DARMISelLowering.cpp1710 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
6006 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6446 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
8000 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
8063 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
8304 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
/external/clang/include/clang/Basic/
Darm_neon.td782 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",

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