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Searched refs:VS1 (Results 1 – 9 of 9) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-move-21.ll53 %VS1 = fadd double %VE0, %Vadd38
55 ret double %VS1
/external/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td61 // Dispatch of an instruction to VS1 that uses four single prec. inputs
69 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
72 // op. has been dispatched to VS1.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td60 // Dispatch of an instruction to VS1 that uses four single prec. inputs
68 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
71 // op. has been dispatched to VS1.
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td60 // Dispatch of an instruction to VS1 that uses four single prec. inputs
68 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
71 // op. has been dispatched to VS1.
/external/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll228 ; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], [[SGPR1]]
230 ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VS1]], [[SGPR0]], [[VK0]]
232 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK1]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Duse-sgpr-multiple-times.ll230 ; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[SGPR1]]
232 ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK0]]
234 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]]
/external/llvm/test/CodeGen/PowerPC/
Dvsx.ll1219 ; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1221 ; CHECK-REG: xxspltw 34, [[VS1]], 0
1230 ; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1231 ; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp2519 const APInt &VS1 = N1->getConstantOperandAPInt(0); in visitADD() local
2520 SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1); in visitADD()
/external/icu/icu4c/source/data/unidata/
Dppucd.txt20532 cp;FE00;na=VARIATION SELECTOR-1;Name_Alias=abbreviation=VS1