1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s 3 4declare float @llvm.fma.f32(float, float, float) #1 5declare double @llvm.fma.f64(double, double, double) #1 6declare float @llvm.fmuladd.f32(float, float, float) #1 7declare float @llvm.amdgcn.div.fixup.f32(float, float, float) #1 8 9 10; GCN-LABEL: {{^}}test_sgpr_use_twice_binop: 11; GCN: s_load_dword [[SGPR:s[0-9]+]], 12; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]] 13; GCN: buffer_store_dword [[RESULT]] 14define amdgpu_kernel void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 { 15 %dbl = fadd float %a, %a 16 store float %dbl, float addrspace(1)* %out, align 4 17 ret void 18} 19 20; GCN-LABEL: {{^}}test_sgpr_use_three_ternary_op: 21; GCN: s_load_dword [[SGPR:s[0-9]+]], 22; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]] 23; GCN: buffer_store_dword [[RESULT]] 24define amdgpu_kernel void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 { 25 %fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1 26 store float %fma, float addrspace(1)* %out, align 4 27 ret void 28} 29 30; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b: 31; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 32; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 33; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 34; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]] 35; GCN: buffer_store_dword [[RESULT]] 36define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 { 37 %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1 38 store float %fma, float addrspace(1)* %out, align 4 39 ret void 40} 41 42; GCN-LABEL: {{^}}test_use_s_v_s: 43; GCN-DAG: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 44; SI: buffer_load_dword [[VA0:v[0-9]+]] 45; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] 46 47; GCN-NOT: v_mov_b32 48 49; VI: buffer_load_dword [[VA0:v[0-9]+]] 50; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] 51 52; GCN-NOT: v_mov_b32 53; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]] 54; GCN-NOT: v_mov_b32 55 56; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]] 57; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]] 58; GCN: buffer_store_dword [[RESULT0]] 59; GCN: buffer_store_dword [[RESULT1]] 60define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float addrspace(1)* %in) #0 { 61 %va0 = load volatile float, float addrspace(1)* %in 62 %va1 = load volatile float, float addrspace(1)* %in 63 %fma0 = call float @llvm.fma.f32(float %a, float %va0, float %b) #1 64 %fma1 = call float @llvm.fma.f32(float %a, float %va1, float %b) #1 65 store volatile float %fma0, float addrspace(1)* %out 66 store volatile float %fma1, float addrspace(1)* %out 67 ret void 68} 69 70; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a: 71; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 72; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 73; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 74; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]] 75; GCN: buffer_store_dword [[RESULT]] 76define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 { 77 %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1 78 store float %fma, float addrspace(1)* %out, align 4 79 ret void 80} 81 82; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a: 83; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 84; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 85; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 86; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]] 87; GCN: buffer_store_dword [[RESULT]] 88define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 { 89 %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1 90 store float %fma, float addrspace(1)* %out, align 4 91 ret void 92} 93 94; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm: 95; GCN: s_load_dword [[SGPR:s[0-9]+]] 96; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0 97; GCN: buffer_store_dword [[RESULT]] 98define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 { 99 %fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1 100 store float %fma, float addrspace(1)* %out, align 4 101 ret void 102} 103 104; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a: 105; GCN: s_load_dword [[SGPR:s[0-9]+]] 106; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]] 107; GCN: buffer_store_dword [[RESULT]] 108define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 { 109 %fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1 110 store float %fma, float addrspace(1)* %out, align 4 111 ret void 112} 113 114; Don't use fma since fma c, x, y is canonicalized to fma x, c, y 115; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a: 116; GCN: s_load_dword [[SGPR:s[0-9]+]] 117; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]] 118; GCN: buffer_store_dword [[RESULT]] 119define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_imm_a_a(float addrspace(1)* %out, float %a) #0 { 120 %val = call float @llvm.amdgcn.div.fixup.f32(float 2.0, float %a, float %a) #1 121 store float %val, float addrspace(1)* %out, align 4 122 ret void 123} 124 125; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_kimm: 126; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]] 127; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000 128; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[VK]] 129; GCN: buffer_store_dword [[RESULT]] 130define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_kimm(float addrspace(1)* %out, float %a) #0 { 131 %fma = call float @llvm.fma.f32(float %a, float %a, float 1024.0) #1 132 store float %fma, float addrspace(1)* %out, align 4 133 ret void 134} 135 136; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s: 137; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]] 138; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]] 139; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 140; GCN: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR]] 141; GCN: buffer_store_dword [[RESULT0]] 142define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s(float addrspace(1)* %out, float %a) #0 { 143 %fma = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1 144 store float %fma, float addrspace(1)* %out 145 ret void 146} 147 148; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s_x2: 149; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 150; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] 151; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 152; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 153; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]] 154; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SK]], [[SK]], [[VGPR1]] 155; GCN: buffer_store_dword [[RESULT0]] 156; GCN: buffer_store_dword [[RESULT1]] 157; GCN: s_endpgm 158define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s_x2(float addrspace(1)* %out, float %a, float %b) #0 { 159 %fma0 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1 160 %fma1 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %b) #1 161 store volatile float %fma0, float addrspace(1)* %out 162 store volatile float %fma1, float addrspace(1)* %out 163 ret void 164} 165 166; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k: 167; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]] 168; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]] 169; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 170; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]] 171; GCN: buffer_store_dword [[RESULT]] 172define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k(float addrspace(1)* %out, float %a) #0 { 173 %fma = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1 174 store float %fma, float addrspace(1)* %out 175 ret void 176} 177 178; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k_x2: 179; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 180; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] 181; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 182; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 183; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]] 184; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]] 185; GCN: buffer_store_dword [[RESULT0]] 186; GCN: buffer_store_dword [[RESULT1]] 187; GCN: s_endpgm 188define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k_x2(float addrspace(1)* %out, float %a, float %b) #0 { 189 %fma0 = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1 190 %fma1 = call float @llvm.fma.f32(float 1024.0, float %b, float 1024.0) #1 191 store volatile float %fma0, float addrspace(1)* %out 192 store volatile float %fma1, float addrspace(1)* %out 193 ret void 194} 195 196; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k: 197; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]] 198; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]] 199; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 200; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]] 201; GCN: buffer_store_dword [[RESULT]] 202define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k(float addrspace(1)* %out, float %a) #0 { 203 %fma = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1 204 store float %fma, float addrspace(1)* %out 205 ret void 206} 207 208; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k_x2: 209; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 210; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]] 211; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]] 212; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000 213; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]] 214; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]] 215; GCN: buffer_store_dword [[RESULT0]] 216; GCN: buffer_store_dword [[RESULT1]] 217; GCN: s_endpgm 218define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(float addrspace(1)* %out, float %a, float %b) #0 { 219 %fma0 = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1 220 %fma1 = call float @llvm.fma.f32(float %b, float 1024.0, float 1024.0) #1 221 store volatile float %fma0, float addrspace(1)* %out 222 store volatile float %fma1, float addrspace(1)* %out 223 ret void 224} 225 226; GCN-LABEL: {{^}}test_s0_s1_k_f32: 227; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb 228; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c 229; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000 230; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[SGPR1]] 231 232; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK0]] 233; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000 234; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]] 235 236; GCN: buffer_store_dword [[RESULT0]] 237; GCN: buffer_store_dword [[RESULT1]] 238define amdgpu_kernel void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, float %b) #0 { 239 %fma0 = call float @llvm.fma.f32(float %a, float %b, float 1024.0) #1 240 %fma1 = call float @llvm.fma.f32(float %a, float %b, float 4096.0) #1 241 store volatile float %fma0, float addrspace(1)* %out 242 store volatile float %fma1, float addrspace(1)* %out 243 ret void 244} 245 246; FIXME: Immediate in SGPRs just copied to VGPRs 247; GCN-LABEL: {{^}}test_s0_s1_k_f64: 248; GCN-DAG: s_load_dwordx2 [[SGPR0:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} 249; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR1_SUB0:[0-9]+]]:[[SGPR1_SUB1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x1d|0x74}} 250; GCN-DAG: v_mov_b32_e32 v[[VK0_SUB1:[0-9]+]], 0x40900000 251; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}} 252 253; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]] 254; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]] 255; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]}} 256 257; Same zero component is re-used for half of each immediate. 258; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000 259; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]}} 260 261; GCN: buffer_store_dwordx2 [[RESULT0]] 262; GCN: buffer_store_dwordx2 [[RESULT1]] 263define amdgpu_kernel void @test_s0_s1_k_f64(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) #0 { 264 %fma0 = call double @llvm.fma.f64(double %a, double %b, double 1024.0) #1 265 %fma1 = call double @llvm.fma.f64(double %a, double %b, double 4096.0) #1 266 store volatile double %fma0, double addrspace(1)* %out 267 store volatile double %fma1, double addrspace(1)* %out 268 ret void 269} 270 271attributes #0 = { nounwind } 272attributes #1 = { nounwind readnone } 273