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Searched refs:VSCALE (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/test/Transforms/LoopVectorize/
Dscalable-loop-unpredicated-body-scalar-tail.ll6 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
7 ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
11 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
12 ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
25 ; CHECKUF1: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
26 ; CHECKUF1: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
37 ; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
38 ; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3
42 ; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
43 ; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-vscale-combine.ll80 ; At IR level, %shl = 2^4 * VSCALE.
81 ; At Assembly level, the output of RDVL is also 2^4 * VSCALE.
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1119 VSCALE, enumerator
DSelectionDAG.h958 return getNode(ISD::VSCALE, DL, VT,
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp174 case ISD::VSCALE: return "vscale"; in getOperationName()
DDAGCombiner.cpp2508 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2516 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2517 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
3457 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
3829 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
8263 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
DSelectionDAG.cpp4739 case ISD::VSCALE: in getNode()
5249 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
5303 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
DLegalizeIntegerTypes.cpp95 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
DSelectionDAGBuilder.cpp3814 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td321 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp4921 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
DAArch64ISelLowering.cpp1058 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
4300 case ISD::VSCALE: in LowerOperation()